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An Infineon Technologies Company
ADM7001 Single Ethernet 10/100M PHY
Datasheet
Version 1.07
Infineon-ADMtek Co Ltd
Information in this document is provided in connection with Infineon-ADMtek Co Ltd products. InfineonADMtek Co Ltd may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined". Infineon-ADMtek Co Ltd reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them The products may contain design defects or errors know as errata, which may cause the product to deviate from published specifications. Current characterized errata are available on request. To obtain latest documentation please contact you local Infineon-ADMtek Co Ltd sales office or visit Infineon-ADMtek Co Ltd's website at http://www.ADMtek.com.tw *Third-party brands and names are the property of their respective owners.
Copyright 2004 by ADMtek Incorporated All Rights Reserved
Infineon-ADMtek Co Ltd
V1.07
About this Manual Intended Audience Structure
This Data sheet contains 6 chapters Chapter 1. Chapter 2. Chapter 3. Chapter 4. Chapter 5. Chapter 6. Product Overview Interface Description Function Description Register Description Electrical Specification Packaging
Revision History
Date Change First release of ADM7001 Register Modifications and Pin updates. The following sections were updated: 1.2, 1.3, 2.1, 2.2.1, 2.2.5, 2.2.7, 2.2.8, 2.2.8, 4.1, 4.2.3-4, 4.2.11-12, 4.3.4, 4.3.9, 4.3.11, 4.3.12, & 4.3.16 30 July 2003 1.03 Updated section 6.2 15 September 2003 1.04 Updated Section 2.2.5, 2.2.8, & 4.2.11 19 February 2004 1.05 Updated table 5.3 16 April 2004 1.06 Removed TQFP packaging 28 April 2004 1.07 Updated Infineon-Infineon-ADMtek Co Ltd logo Detailed revision information is available on request.
05 March 2003 08 April 2003 24 July 2003
Version 1.0 1.01 1.02
Customer Support
Infineon-ADMtek Co Ltd, 2F, No.2, Li-Hsin Rd., Science-based Industrial Park, Hsinchu, 300, Taiwan, R.O.C.
Sales Information
Tel + 886-3-5788879 Fax + 886-3-5788871 ADM7001
Infineon-ADMtek Co Ltd
V1.07
Table of Contents
Chapter 1 Product Overview ........................................................................................ 1-1 1.1 Overview.......................................................................................................... 1-1 1.1.1 Product Order Information...................................................................... 1-1 1.2 Features ............................................................................................................ 1-1 1.3 Block Diagram ................................................................................................. 1-2 1.4 Abbreviations and Acronyms .......................................................................... 1-3 1.5 Conventions ..................................................................................................... 1-4 1.5.1 Data Lengths............................................................................................ 1-4 1.5.2 Register Type Descriptions ...................................................................... 1-4 1.5.3 Pin Type Descriptions.............................................................................. 1-5 Chapter 2 Interface Description ................................................................................... 2-1 2.1 Pin Diagram ..................................................................................................... 2-1 2.2 Pin Description................................................................................................. 2-2 2.2.1 Twisted Pair Interface, 5 pins.................................................................. 2-2 2.2.2 Digital Power/Ground, 7 pins.................................................................. 2-2 2.2.3 Ground and Power, 5 pins ....................................................................... 2-2 2.2.4 Clock Input, 2 pins ................................................................................... 2-3 2.2.5 MII/RMII/GPSI Interface, 16 pins ........................................................... 2-3 2.2.6 Reset Pin .................................................................................................. 2-6 2.2.7 Control Signals, 6 pins............................................................................. 2-6 2.2.8 LED Interface, 4 pins............................................................................... 2-7 2.2.9 Regulator Control .................................................................................... 2-8 Chapter 3 Function Description ................................................................................... 3-1 3.1 10/100M PHY Block ....................................................................................... 3-1 3.1.1 100Base-X Module................................................................................... 3-1 3.1.2 100Base-TX Receiver............................................................................... 3-2 3.1.3 100Base-TX Transmitter.......................................................................... 3-7 3.1.4 100Base-FX Receiver............................................................................... 3-7 3.1.5 100Base-FX Transmitter.......................................................................... 3-7 3.1.6 10Base-T Module ..................................................................................... 3-7 3.1.7 Operation Modes ..................................................................................... 3-7 3.1.8 Manchester Encoder/Decoder ................................................................. 3-8 3.1.9 Transmit Driver and Receiver ................................................................. 3-8 3.1.10 Smart Squelch .......................................................................................... 3-8 3.1.11 Carrier Sense ........................................................................................... 3-9 3.1.12 Collision Detection .................................................................................. 3-9 3.1.13 Jabber Function ....................................................................................... 3-9 3.1.14 Link Test Function ................................................................................. 3-10 3.1.15 Automatic Link Polarity Detection ........................................................ 3-10 3.1.16 Clock Synthesizer ................................................................................... 3-10 3.1.17 Auto Negotiation .................................................................................... 3-10 3.1.18 Auto Negotiation and Speed Configuration........................................... 3-11 3.2 MAC Interface ............................................................................................... 3-11 3.2.1 Reduced Media Independent Interface (RMII) ...................................... 3-12 3.2.2 Receive Path for 100M........................................................................... 3-12 ADM7001 i
Infineon-ADMtek Co Ltd 3.2.3 Receive Path for 10M............................................................................. 3-13 3.2.4 Transmit Path for 100M ........................................................................ 3-14 3.2.5 Transmit Path for 10M .......................................................................... 3-14 3.2.6 Media Independent Interface (MII) ....................................................... 3-15 3.2.7 Receive Path for MII.............................................................................. 3-15 3.2.8 Transmit Path For MII........................................................................... 3-17 3.2.9 General Purpose Serial Interface (GPSI).............................................. 3-17 3.2.10 Receive Path for GPSI ........................................................................... 3-18 3.2.11 Transmit Path for GPSI ......................................................................... 3-18 3.3 LED Display .................................................................................................. 3-18 3.4 Management Register Access ........................................................................ 3-19 3.4.1 Preamble Suppression ........................................................................... 3-20 3.4.2 Reset Operation ..................................................................................... 3-20 3.5 Power Management ....................................................................................... 3-21 3.6 Voltage Regulator .......................................................................................... 3-22 Chapter 4 Register Description .................................................................................... 4-1 4.1 Register Mapping............................................................................................. 4-1 4.2 Register Bit Mapping....................................................................................... 4-2 4.2.1 Register #0h -- Control Register.............................................................. 4-2 4.2.2 Register #1h - Status Register ................................................................. 4-2 4.2.3 Register #2h - PHY ID Register (002E) .................................................. 4-2 4.2.4 Register #3h - PHY ID Register (CC62) ................................................. 4-2 4.2.5 Register #4h - Advertisement Register .................................................... 4-2 4.2.6 Register #5h - Link Partner Ability Register........................................... 4-2 4.2.7 Register #6h - Auto Negotiation Expansion Register.............................. 4-2 4.2.8 Register #7h - # Fh Reserved .................................................................. 4-2 4.2.9 Register #10h - PHY Configuration Register.......................................... 4-2 4.2.10 Register #11h - 10M Configuration Register.......................................... 4-3 4.2.11 Register #12h - 100M Configuration Register........................................ 4-3 4.2.12 Register #13h - LED Configuration Register.......................................... 4-3 4.2.13 Register #14h - Interrupt Enable Register .............................................. 4-3 4.2.14 Register #16h - PHY Generic Status Register......................................... 4-3 4.2.15 Register #17h - PHY Specific Status Register......................................... 4-3 4.2.16 Register #18h - Recommend Value Storage Register ............................. 4-3 4.2.17 Register #19h - Interrupt Status Register................................................ 4-3 4.2.18 Register #1dh - Receive Error Counter .................................................. 4-3 4.2.19 Register #1fh - Chip ID (8125)................................................................ 4-4 4.3 Register Description......................................................................................... 4-4 4.3.1 Control (Register 0h) ............................................................................... 4-4 4.3.2 Status (Register 1h).................................................................................. 4-6 4.3.3 PHY Identifier Register (Register 2h)...................................................... 4-8 4.3.4 PHY Identifier Register (Register 3h)...................................................... 4-8 4.3.5 Advertisement (Register 4h)..................................................................... 4-8 4.3.6 Auto Negotiation Link Partner Ability (Register 5h)............................... 4-9 4.3.7 Auto Negotiation Expansion Register (Register 6h).............................. 4-10 4.3.8 Register Reserved (Register 7h-Fh)....................................................... 4-11
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Infineon-ADMtek Co Ltd 4.3.9 Generic PHY Configuration Register (Register 10h) ............................ 4-11 4.3.10 PHY 10M Module Configuration Register (Register 11h) .................... 4-12 4.3.11 PHY 100M Module Control Register (Register 12h)............................. 4-13 4.3.12 LED Configuration Register (Register 13h) .......................................... 4-14 4.3.13 Interrupt Enable Register (Register 14h) .............................................. 4-15 4.3.14 PHY Generic Status Register (Register 16h) ......................................... 4-16 4.3.15 PHY Specific Status Register (Register 17h) ......................................... 4-17 4.3.16 PHY Recommend Value Status Register (Register 18h) ........................ 4-18 4.3.17 Interrupt Status Register (Register 19h) ................................................ 4-19 4.3.18 Receive Error Counter Register (Register 1Dh).................................... 4-20 4.3.19 Chip ID Register (Register 1Fh)............................................................ 4-20 Chapter 5 Electrical Specification................................................................................ 5-1 5.1 DC Characterization......................................................................................... 5-1 5.1.1 Absolute Maximum Rating....................................................................... 5-1 5.1.2 Recommended Operating Conditions ...................................................... 5-1 5.1.3 DC Electrical Characteristics for 2.5V Operation .................................. 5-1 5.2 AC Characterization......................................................................................... 5-2 5.2.1 XI/OSCI (Crystal/Oscillator) Timing (In MII Mode)............................... 5-2 5.3 RMII Timing.................................................................................................... 5-3 5.3.1 REFCLK Input Timing (XI in RMII Mode).............................................. 5-3 5.3.2 REFCLK Output Timing (CLKO50 in RMII Mode) ................................ 5-4 5.3.3 RMII Transmit Timing ............................................................................. 5-5 5.3.4 RMII Receive Timing ............................................................................... 5-6 5.4 MII Timing....................................................................................................... 5-7 5.4.1 RXCLK Clock Timing .............................................................................. 5-7 5.4.2 MII Receive Timing.................................................................................. 5-8 5.4.3 TXCLK Output Timing............................................................................. 5-9 5.4.4 MII Transmit Timing.............................................................................. 5-10 5.5 GPSI Timing .................................................................................................. 5-11 5.5.1 GPSI Receive Timing ................................................................................. 5-11 5.5.2 GPSI Transmit Timing ............................................................................... 5-12 5.6 Power On Configuration Timing ................................................................... 5-14 Chapter 6 Packaging...................................................................................................... 6-1 6.1 ADM7001 Low Profile Quad Flat Package (LQFP) 48 Pin ............................ 6-1
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List of Figures
Figure 1-1 ADM7001 Block Diagram............................................................................. 1-2 Figure 2-1 ADM7001 48 Pin Diagram ............................................................................ 2-1 Figure 3-1 100Base-X Block Diagram and Data Path..................................................... 3-2 Figure 3-2 10Base-T Block Diagram and Data Path ....................................................... 3-9 Figure 3-3 RMII Signal Diagram................................................................................... 3-12 Figure 3-4 RMII Reception Without Error .................................................................... 3-13 Figure 3-5 RMII Reception with False Carrier (100M Only)........................................ 3-13 Figure 3-6 RMII Reception with Symbol Error............................................................. 3-13 Figure 3-7 10M RMII Receive Diagram ....................................................................... 3-13 Figure 3-8 100M RMII Transmit Diagram.................................................................... 3-14 Figure 3-9 10M RMII Transmit Diagram...................................................................... 3-14 Figure 3-10 MII Signal Diagram ................................................................................... 3-15 Figure 3-11 MII Receive Without Error ........................................................................ 3-16 Figure 3-12 MII Receive With False Carrier................................................................. 3-16 Figure 3-13 MII Receive With Symbol Error (100M Only).......................................... 3-16 Figure 3-14 MII Transmission ....................................................................................... 3-17 Figure 3-15 MII Transmit with Collision (Half Duplex Only)...................................... 3-17 Figure 3-16 GPSI Signal Diagram................................................................................. 3-17 Figure 3-17 GPSI Receive Diagram .............................................................................. 3-18 Figure 3-18 GPSI Transmit Diagram............................................................................. 3-18 Figure 3-19 SMI Read Operation .................................................................................. 3-20 Figure 3-20 SMI Write Operation.................................................................................. 3-21 Figure 3-21 Medium Detect Power Management Flow Chart....................................... 3-22 Figure 3-22 Power and Ground Filtering....................................................................... 3-23 Figure 5-1 Crystal/Oscillator Timing............................................................................... 5-2 Figure 5-2 REFCLK Input Timing .................................................................................. 5-3 Figure 5-3 REFCLK Output Timing................................................................................ 5-4 Figure 5-4 RMII Transmit Timing................................................................................... 5-5 Figure 5-5 RMII Receive Timing .................................................................................... 5-6
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List of Tables
Table 3-1 Look-up Table for translating 5B Symbols into 4B Nibbles........................... 3-5 Table 3-2 Channel Configuration .................................................................................. 3-15 Table 3-3 Speed LED Display ....................................................................................... 3-19 Table 3-4 Duplex LED Display ..................................................................................... 3-19 Table 3-5 Activity/Link LED Display ........................................................................... 3-19 Table 3-6 Cable Distance LED Display......................................................................... 3-19 Table 5-1 Electrical Absolute Maximum Rating ............................................................. 5-1 Table 5-2 Recommended Operating Conditions.............................................................. 5-1 Table 5-3 DC Electrical Characteristics for 3.3V Operation........................................... 5-1 Table 5-4 Crystal/Oscillator Timing................................................................................ 5-2 Table 5-5 REFCLK Input Timing.................................................................................... 5-3 Table 5-6 REFCLK Output Timing................................................................................. 5-4 Table 5-7 RMII Transmit Timing .................................................................................... 5-5 Table 5-8 RMII Receive Timing...................................................................................... 5-6
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Product Review
Chapter 1
1.1 Overview
Product Overview
ADM7001, is a single chip one port 10/100M PHY, designed for today's low cost and low power dual speed application. It supports auto sensing 10/100 Mbps ports with onchip clock recovery and base line wander correction including integrated MLT-3 functionality for 100 Mbps operation and also supports Manchester Code Converter with on chip clock recovery circuitry for 10 Mbps functionality. Meanwhile, it provides Medium Independent Interface (MII), Reduced Medium Independent Interface (RMII) and General Purpose Serial Interface (GPSI), three different interfaces different application. For today's IA (Information Application), ADM7001 supports "Auto Cross Over Detection" function to eliminate the technical barrier between networking and end user. With the aid of this auto cross over detection function, Plug-n-Play feature can be easily applied to IA relative products. The major design target for ADM7001 is to reduce the power consumption and system radiation for the whole system. With the aid of this low power consumption and low radiation chip, the fan and on-system power supply can be removed to save the total manufacture cost and make SOHO application achievable. 1.1.1 Product Order Information The ADM7001 comes in two packaging formats as follows: 6.1 ADM7001 Low Profile Quad Flat Package (LQFP)
1.2
Features
* * * * * * * * * * *
IEEE 802.3 compatible 10BASE-T and 100BASE-T physical layer interface and ANSI X3.263 TP-PMD compatible transceiver Single chip, integrated physical layer and transceivers for 10BASE-T and 100BASETX function. Medium Independent Interface (MII), Reduced MII (RMII) and General Purpose Serial Interface (GPSI) for high port count switch Built-in 10Mbit transmit filter 10Mbit PLL, exceeding tolerances for both preamble and data jitter 100Mbit PLL, combined with the digital adaptive equalizer and performance up to 120 meters for UTP 5. 125MHz Clock Generator and Timing Recovery Integrated Base Line Wander Correction Carrier Integrity Monitor function supported Support FEFI when Auto Negotiation disabled Support Auto MDIX function for Plug-and-Play
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* * * * * * * * * * *
Product Review IEEE 802.3u Clause 28 compliant auto negotiation for full 10 Mbps and 100 Mbps control. Supports programmable LED For different Switch Application and Power On LED Self Test Supports Cable Length Indication both in MII Register and LED (Programmable) Supports PECL interface for fiber connection Supports TP vs. FX Medium Converter function Supports Fault Propagation function for medium converter Supports 10K Bytes Jumbo Packet with Clock Skew 150 ppm Built-in Clock Generator and Power On Reset Signal to save system cost 48 LQFP without regulator Support Power saving function Support Parallel LED output
1.3
Block Diagram
Figure 1-1 ADM7001 Block Diagram
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Product Review
1.4
Abbreviations and Acronyms
ANSI BER COL CRS CRSDV CTL DSP DUPCOL ESD FEFI FIFO FLP FX GPSI TP TX RX IA LFSR LNKACT LQFP LVTTL MAC MD MDC MDIO NRZ NRZI OP PCS PECL PHY PHYADDR PMA PMD PNP PQFP REFCLK RF MII RMII RXCLK RXD RXDV American National Standards Institute Bit Error Rate Collision Carrier Sense Carrier Sense and Data Valid Crystal Digital Signal Processor Duplex and Collision End of Stream Delimiter Far End Fault Indication First In First Out Fast Link Pulse Fiber General Purpose Serial Interface Twisted Pair Transmit Receive Information Application Linear Feedback Shifter Register Link and Activity Low Profile Quad Flat Package Low Voltage TTL Level Media Access Controller Medium Detect Management Data Clock Management Data Input/Output None Return to Zero None Return to Zero Inverter Operation Code Physical Coding Sub-layer Pseudo Emitter Couple Logic Physical Layer PHY Address Physical Medium Attachment Physical Medium Dependent A type of Transistor Plastic Quad Flat Pack Reference Clock Remote Fault Media Independent Interface Reduced Media Independent Interface Receive Clock Receive Data Receive Data Valid
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ADM7001 RXER RXN RXP SDN SDP SELFX SMI SOHO SQE SSD GPSI TA TDR TP-PMD TTL TXCLK TXD TXEN TXER TXN TXP /J/K /T/R PHYDIG TRXANA Receive Data Error Receive Negative (Analog receive differential signal) Receive Positive (Analog receive differential signal) Signal Detect Negative (Fiber signal detect) Signal Detect Positive (Fiber signal detect) Select Fiber Serial Management Interface Small Office and Home Office Signal Quality Error Start of Stream Delimiter General Purpose Serial Interface Turn Around Time Domain Reflectometry Twisted Pair Physical Medium Dependent Transistor Transistor Logic MII Transmission Clock Transmission Data Transmission Enable Transmission Error Transmission Negative Transmission Positive 5B signal to detect the start of a frame 5B signal to detect the end of a frame Internal Digital Block to Handle PHY relative functions Internal Analog Block contains both TX and RX Function
Product Review
1.5
1.5.1
Conventions
Data Lengths qword dword word byte nibble 64-bits 32-bits 16-bits 8 bits 4 bits Description Read Only Read and Write capable Self-clearing Latching low, unlatch on read Latching high, unlatch on read Clear On Read
1.5.2
Register Type Descriptions Register Type RO R/W SC LL LH COR
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ADM7001 1.5.3 Pin Type Descriptions Pin Type I: O: I/O: OD: SCHE: PU: PD:
Product Review
Description Input Output Bi-directional Open drain Schmitt Trigger Pull Up Pull Down
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Interface Description
Chapter 2
2.1
Interface Description
Pin Diagram
PHYAD4/RXD0 PYYAD3/RXD1 PHYAD2/RXD2 PHYAD1/RXD3 MDC MDIO RESET_N VCC33IN XI XO TEST1 GNDIK 48 47 46 45 44 43 42 41 40 39 38 37 1 2 3 4 5 6 7 8 9 10 11 12
VCCO_25 GNDIK RXDV/CRSDV/DIS_AMDIX RMII_EN/RX_CLK ISOLATE/RXER GNDO VCCIK_25 TXER TXCLK TXEN TXD0 TXD1
ADM7001 48 Pin
36 35 34 33 32 31 30 29 28 27 26 25
VCC25OUT(CORE) TXP TXN GNDPLL VCCPLL_25 RTX TEST0 GNDTR SD/FXEN RXP RXN VCCA_25
13 14 15 16 17 18 19 20 21 22 23 24 PWRDOWN_N ANEN/COLLED DUPFUL/DUPLED SPD100/SPDLED LNKACT PHYAD0/INTR VCCO_2.5 GNDO CRS COL/GPSI TXD3 TXD2
Figure 2-1 ADM7001 48 Pin Diagram
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Interface Description
2.2
Pin Description
Note: For those pins, which have multiple functions, pin name is separated by slash ("/"). If not specified, all signals are default to digital signals. Please refer to section `1.5.3 Pin Type Descriptions' for an explanation of pin abbreviations.
2.2.1 Twisted Pair Interface, 5 pins
Pin # 35 34 27 26 28 Pin Name TXP TXN RXP RXN Power On Setting FXEN Fiber Mode SDP Type I/O, Analog I/O, Analog I/O, Analog I/O, Analog I, Analog Description Twisted Pair Transmit Output Positive. Twisted Pair Transmit Output Negative. Twisted Pair Receive Input Positive. Twisted Pair Receive Input Negative. Fiber Enable. Value on this pin will be latched by ADM7001 during power on reset as fiber select signal. 0: Twisted Pair Mode 1: Fiber Optic Mode 100BASE-FX Signal Detect. After power on reset stage, this pin acts as signal detect signal from external fiber optic transceiver in case FXEN is detected as high during power on reset. 0: No signal detected 1: Signal
2.2.2 Digital Power/Ground, 7 pins
Pin # 6, 17 2, 37 1, 18 7 Pin Name GNDO GNDIK VCCO_25 VCCIK_25 Type Digital Ground Digital Ground Digital Power Digital Power Pin Description Ground used by 3.3V I/O. Ground used by Core. 2.5V Power Used by Digital I/O Pad. 2.5V Power used by Core
2.2.3 Ground and Power, 5 pins
Pin # 41 36 29 25 Pin Name VCC3IN VCC25OUT GNDTR VCCA_25 Type Analog Power Analog Power Analog Ground Analog Power Description 3.3V Power input to ADM7001 and used by built-in 3.3V to 2.5V regulator. 2.5V Power output by ADM7001. Maximum Supply current from this pin is 200 mA. Analog Ground Pad Analog 2.5V Power
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32 VCCPLL_25
Interface Description
Analog Analog 2.5V Power used by Clock Generator module Power
2.2.4
Clock Input, 2 pins
Pin # 40 39 Pin Name XI/OSCI XO Pin Description Crystal/Oscillator input. 25M Crystal/Oscillator Input in MII mode and 50M Clock input in RMII mode (Also called REFCLK in RMII Mode) O, CTL Crystal output. When 25M Oscillator is used, this pin should left unconnected. Capable of driving one XI input for multiple port application. Type I, CTL
2.2.5
MII/RMII/GPSI Interface, 16 pins
Pin # 9 Pin Name MII Mode TXCLK Type O, 16mA Pin Description MII Transmit Clock. 25M Clock output in 100BASE-X mode and 2.5M Clock output for 10BASE-T mode. This clock is continuously driven output and generated from XI. Before Speed is recognized, this pin drives out continuous 25M clock. N/A. GPSI Transmit Clock. 10M Clock output in 10BASE-T mode. I, TTL, PD Transmit Data. Nibble-wide transmit data stream in MII mode. These four bits are synchronous to the rising edge of TXCLK and TXD[3] is the most significant bit. Di-bits Transmit Data. TXD0 and TXD1 for the di-bits that are transmitted and are driven synchronously to REFCLK. TXD[1] is the MSB. Note that in 100Mb/s mode, TXD can change once per REFCLK cycle, whereas in 10Mb/s mode, TXD must be held steady for 10 consecutive REFCLK cycles. TXD[3] and TXD[2] are not used in RMII Mode, left unconnected or pull down externally for normal operation. Serial Transmit Data. TXD0 for the designated port inputs the data that is transmitted and is driven synchronously to TXCLK in 10Mb/s mode. When ADM7001 is programmed into GPSI mode, TXD[3:1] should be left unconnected or pull down externally for normal operation. Transmit Enable. Transmit Enable to indicate that the data on TXD[3:0] is valid. Transmit Enable. TXEN indicates that the di-bit on TXD is valid and it is driven synchronously to REFCLK. Transmit Enable. Transmit Enable to indicate that the data on TXD0 is valid. I, TTL, Transmit Error. Active high signal to indicate that there is PD error condition requested by MAC. Transmit Error. Active high signal to indicate that there is error condition requested by MAC.
RMII Mode TXCLK GPSI Mode TXCLK MII Mode TXD[3:0] RMII Mode TXD[1:0]
14, 13, 12, 11
GPSI Mode TXD
10
MII Mode TXEN RMII Mode TXEN GPSI Mode TXEN MII Mode TXER RMII Mode TXER
I, TTL, PD
8
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Pin # Pin Name GPSI Mode LOW Power On Setting RMII_EN Type Pin Description Keep Low in GPSI Mode.
Interface Description
4
RMII Enable. Used to select MII or RMII operation. The I, LVTTL, default value during power on reset is 0 (Before RMII_EN and GPSI value is determined) PD 0: MII mode 1: RMII Mode O, 16mA MII Receive Clock. 25M Clock output in 100BASE-X mode, 2.5M Clock output for 10BASE-T MII mode. This clock is recovered from the received data on the cable input. Due to recovered from incoming receive data, it is possible that RXCLK starts running yet RXDV keeps low for a while. During power on reset, there is no receiving clock driven by ADM7001. RMII 50M Clock Output. This pin outputs continuous 50M clock in RMII mode. To reduce the BOM cost for system application, user can connect this pin directly to REFCLK to proper RMII operation. GPSI Receive Clock. 10M clock for 10BASE-T GPSI mode. This clock is recovered from the received data on the cable input. Due to recovered from incoming receive data, it is possible that RXCLK starts running yet CRS keeps low for a while. During power on reset, there is no receiving clock driven by ADM7001.
MII Mode RX_CLK
RMII Mode CLKO50
GPSI Mode RX_CLK
3
Note: that clock on this pin will not be active during power on reset due to power on setting. Power On I, LVTTL, Disable Auto Crossover Function. Value on this pin will be Setting PD latched by ADM7001 to select Auto Cross-Over Function. DIS_AMDIX_EN 0: Enable Auto Crossover. 1: Disable Auto Crossover. MII Mode RXDV RMII Mode CRSDV O, 8mA O, 8mA MII Receive Data Valid. Active high signal to indicate that the data on RXD[3:0] is valid. Synchronous to the rising edge of RXCLK in MII mode. RMII Carrier Sense/Receive Data Value. Represents Receive Carrier Sense and Data Valid in RMII mode. CRSDV asserts when the receive medium is non-idle. The assertion of CRSDV is asynchronous to REFCLK. At the de-assertion of carrier, CRSDV de-asserts synchronously to REFCLK only on the first di-bit of RXD. If there is still data in the FIFO not yet presented onto RXD, then on the second di-bit of RXD, CRSDV is asserted synchronously to REFCLK. The toggling of CRSDV_P on the first and second di-bit continues until all the data in the FIFO is presented onto RXD. CRSDV is asserted for the duration of carrier activity for a false carrier event. Keep Low in GPSI Mode.
GPSI Mode LOW
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Pin # 45, 46, 47, 48 Pin Name Power On Setting PHYAD[1:4] MII Mode RXD[3:0] RMII Mode RXD[1:0]
Interface Description
Type Pin Description I, TTL, PHY Address Select. Value on these 4 pins combined with PHYAD0 will be stored into ADM7001 as PHY physical address PD during power on reset. After power on reset, these 4 pins are output. O, 8mA O, 8mA MII Receive Data. Nibble-wide receive data stream in MII mode. These four bits are synchronous to the rising edge of RX_CLK and RXD[3] is the most significant bit. RMII Receive Data. RXD0 and RXD1 for the di-bits that are received and are driven synchronously to REFCLK. RXD[1] is the MSB. Note that in 100Mb/s mode, RXD can change once per REFCLK cycle, whereas in 10Mb/s mode, RXD must be held steady for 10 consecutive REFCLK cycles. RXD[3:2] have not used in this mode. GPSI Receive Data. RXD0 for the designated port inputs the data that is transmitted and is driven synchronously to RX_CLK in 10Mb/s mode. RXD[3:1] have not used in this mode. ISOLATE. Value on this pin will be latched by ADM7001 during power on reset. 0: Normal Operation 1: All MII outputs are tri-stated. All MII Inputs(TXD, TXEN, TXER) are ignored . MII Receive Error. Active high signal to indicate that there is error condition detected by ADM7001. When error is detected, RXER will be high and maintains high until RXDV is deasserted. RMII Receive Error. Active high signal to indicate that there is error condition detected by ADM7001. When error is detected, RXER will be high and maintains high until CRSDV is deasserted. No operation in GPSI Mode. I PD GPSI Mode Select. Value on this pin will be sampled by ADM7001 during power on reset to form GPSI internal control signal. Together with RMII_EN, these two pins form three possible internal supported by ADM7001 RMII_EN GPSI Interface 0 0 MII 0 1 GPSI (1M8) 1 x RMII GPSI/MII Collision. In half duplex mode, active high to indicate that there is collision on the medium. In full duplex mode, this pin will keep low all the time. Not Available. I, Repeater Mode. Value on this pin will be latched by ADM7001 LVTTL, during power on reset as repeater mode
GPSI Mode RXD 5 Power On Setting ISOLATE
O, 8mA I, TTL PD
MII Mode RXER
O, 4mA
RMII Mode, RXER
O, 4mA
15
GPSI Mode, N/A Power On Setting GPSI
GPSI/MII Mode COL RMII Mode N/A Power On Setting
O, 8mA
16
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Pin # Pin Name REPEATER Type PD
Interface Description
Pin Description 0: SW/NIC mode, CRS will be asserted according to RX/TX in half duplex mode 1: REPEATER mode. CRS will be asserted only in RX mode in half duplex operation. MII Carrier Sense. This bit indicates that there is carrier sense presented on the medium. Note that in half duplex mode, this pin will also be asserted high by ADM7001 under transmit condition. This pin is asynchronous to RX_CLK. Not Available GPSI Carrier Sense. This bit indicates that there is carrier sense presented on the medium. Note that in half duplex mode, this pin will also be asserted high by ADM7001 under transmit condition. This pin is asynchronous to RX_CLK.
MII Mode CRS
O, 8mA
RMII Mode N/A GPSI Mode CRS
2.2.6
Reset Pin
Pin # 42 Pin Name RESET# Type I, SCHE Description Reset Signal. Active low to bring ADM7001 into reset condition. Recommend keeping low for at least 200 ms to ensure the stability of the system after power on reset.
2.2.7 Control Signals, 6 pins
Pin # 43 Pin Name MDIO Type I/O, LVTTL, PU I, LVTTL Pin Description Management Data. MDIO transfers management data in and out of the device synchronous to MDC. Management Data Reference Clock. A non-continuous clock input for management usage. ADM7001 will use this clock to sample data input on MDIO and drive data onto MDIO according to rising edge of this clock. PHY Address bit 0. See RXD[3:0] description.
44
MDC
19
Power On Setting PHYAD0 MII/RMII/GPSI Mode INTR#
I, LVTTL, PU
24
PWRDOWN#
Interrupt. Default active low signal to indicate that there is interrupt event in SMI register. Active value of interrupt signal can be configured by register 18.1. Only available when interrupt mode is selected. Low Power Operation. I, LVTTL, 0: ADM7001 in low power mode operation. All blocks except the energy detection and crystal oscillator are de-activated. PU 1: ADM7001 in normal mode operation. Note: When RESET# is reset to 0 and PWRDOWN# is set to 0, whole ADM7001 blocks will be disabled. Industrial Test Pin. Keeps low for normal operation.
38, 30
TEST[1:0]
I, LVTTL, PD
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Interface Description
2.2.8
LED Interface, 4 pins
Pin # 20 Pin Name Reserved LNKACT 21 Power On Setting SPD100 Type Pin Description I, TTL, Reserved PU O, 8mA I, TTL PU, Link/Activity LED. Active low (Note) 100ms (blink 100ms) to indicate that there is transmit or receive activity after Link Up. Keeps high all the time when link is failed. Recommend 100M Operation. This bit is only available in TP mode. Together with ANEN to form speed mode select for ADM7001: ANEN SPD100 Mode 0 0 Force 10BASE-T Mode 0 1 Force 100BASE-TX Mode 1 0 10M Capability 1 1 10/100M Capability Speed LED. (Note) 0: 100M 1: 10M Cable Length LED. When FXEN is low and MII register 18.2 DIS_CABLEN_LED is set to 0, this pin together with COLLED and LNKACTLED form cable length information on twisted pair. NOTE: That the following indication assume recommend value on SPDLED, COLLED and LNKACTLED is high, when corresponding bit's power on setting bit is 0, polarity of corresponding bit will be inverted. SPDLED COLLED LNKACTLED Cable Length 110 > 140 meters or Link Failed 110 0 - 40 meters 100 40 - 80 meters 000 80 - 120 meters *** (FLASHED) Reserved Note: When recommend value during power on is high, then this signal is active low; if the recommend value is low, then this signal is active high. Duplex Control. This pin is only available when auto negotiation is disabled. ANEN DUPFUL Mode 0 0 Force to Half Duplex Mode 0 1 Force to Full Duplex Mode 1 0 Half Duplex Capability 1 1 Full/Half Duplex Capability Duplex LED. (Note) 0: Full Duplex 1: Half Duplex Note: When recommend value during power on is high, then
Normal Mode SPDLED
O, 8mA
22
Power On Setting DUPFUL
I, TTL PU,
Normal Mode DUPLED
O, 8mA
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ADM7001
Pin # Pin Name Type
Interface Description
Pin Description this signal is active low; if the recommend value is low, then this signal is active high. This rule also applies to Cable Length indication Auto Negotiation Enable. This bit is only available in TP mode. 0: Disable Auto Negotiation 1: Enable Auto Negotiation Collision LED. Keep high (Note) when ADM7001 is in full duplex mode and will blink 100 ms when collision condition is detected in half duplex mode. Note: When recommend value during power on is high, then this signal is active low; if the recommend value is low, then this signal is active high.
23
Power On Setting ANEN Normal Mode COLLED
I, TTL PU,
O, 8mA
2.2.9
Regulator Control
Pin # 31 Pin Name RTX Type Description I, Constant Voltage Reference. Analog External 1.1k1% resistor connection to ground.
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Function Description
Chapter 3
Function Description
ADM7001 integrates 100Base-X physical sub layer (PHY), 100Base-TX physical medium dependent (PMD) transceivers, and complete 10Base-T modules into a single chip for both 10 Mbps and 100 Mbps Ethernet operations. It also supports 100Base-FX operation through external fiber-optic transceivers. The device is capable of operating in either full-duplex mode or half-duplex mode in either 10 Mbps or 100 Mbps operation. Operational modes can be selected by hardware configuration pins, software settings of management registers, or determined by the on-chip auto negotiation logic. The 10Base-T section of the device consists of the 10 Mbps transceiver module with filters and a Manchester ENDEC module. ADM7001 consists of seven kinds of major blocks: * 10/100M PHY Blocks * MAC Interface * LED Display * SMI * Power Management * Clock Generator * Voltage Regulator Each 10/100M PHY block contains: * 10M PHY block * 100M PHY block * Auto-negotiation * Other Digital Control Blocks
3.1
10/100M PHY Block
The 100Base-X section of the device implements he following functional blocks: * 100Base-X physical coding sub-layer (PCS) * 100Base-X physical medium attachment (PMA) * Twisted-pair PMD (TP-PMD) transceiver The 100Base-X and 10Base-T sections share the following functional blocks: * Clock synthesizer module * MII Registers * IEEE 802.3u auto negotiation
The interfaces used for communication between PHY block and switch core is MII interface. 3.1.1 100Base-X Module ADM7001 implements 100Base-X compliant PCS and PMA and 100Base-TX compliant TP-PMD as illustrated in Figure 3-1. Bypass options for each of the major functional
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Function Description blocks within the 100Base-X PCS provides flexibility for various applications. 100 Mbps PHY loop back is included for diagnostic purpose.
3.1.2 100Base-TX Receiver For 100Base-TX operation, the on-chip twisted pair receiver that consists of a differential line receiver, an adaptive equalizer and a base-line wander compensation circuits detects the incoming signal.
ADM7001 uses an adaptive equalizer that changes filter frequency response in accordance with cable length. The cable length is estimated based on the incoming signal strength. The equalizer tunes itself automatically for any cable length to compensate for the amplitude and phase distortions incurred from the cable. The 100Base-X receiver consists of functional blocks required to recover and condition the 125 Mbps receive data stream. The ADM7001 implements the 100Base-X receiving state machine diagram as given in ANSI/IEEE Standard 802.3u, Clause 24. The 125 Mbps receive data stream may originate from the on-chip twisted-pair transceiver in a 100Base-TX application. Alternatively, the receive data stream may be generated by an external optical receiver as in a 100Base-FX application.
Figure 3-1 100Base-X Block Diagram and Data Path
The receiver block consists of the following functional sub-blocks: * A/D Converter * Adaptive Equalizer and Timing Recovery Module * NRZI/NRZ and Serial/Parallel Decoder * De-scrambler * Symbol Alignment Block Infineon ADMtek Co Ltd 3-2
ADM7001
* * * *
Function Description Symbol Decoder Collision Detect Block Carrier Sense Block Stream Decoder Block
A/D Converter High performance A/D converter with 125M sampling rate converts signals received on RXP/RXN pins to 6 bits data streams; besides it possess auto-gain-control capability that will further improve receive performance especially under long cable or harsh detrimental signal integrity. Due to high pass characteristic on transformer, built in baseline-wander correcting circuit will cancel it out and restore its DC level. Adaptive Equalizer and timing Recovery Module All digital design is especial immune from noise environments and achieves better correlations between production and system testing. Baud rate Adaptive Equalizer/Timing Recovery compensates line loss induced from twisted pair and tracks far end clock at 125M samples per second. Adaptive Equalizer implemented with Feed forward and Decision Feedback techniques meet the requirement of BER less than 10-12 for transmission on CAT5 twisted pair cable ranging from 0 to 140 meters. NRZI/NRZ and Serial/Parallel Decoder The recovered data is converted from NRZI to NRZ. The data is not necessarily aligned to 4B/5B code group's boundary. Data De-scrambling The de-scrambler acquires synchronization with the data stream by recognizing idle bursts of 40 or more bits and locking its deciphering Linear Feedback Shift Register (LFSR) to the state of the scrambling LFSR. Upon achieving synchronization, the incoming data is XORed by the deciphering LFSR and de-scrambled.
In order to maintain synchronization, the de-scrambler continuously monitors the validity of the unscrambled data that it generates. To ensure this, a link state monitor and a hold timer are used to constantly monitor the synchronization status. Upon synchronization of the de-scrambler the hold timer starts a 722 us countdown. Upon detection of at least 6 idle symbols (30 consecutive "1") within the 722 us period, the hold timer will reset and begin a new countdown. This monitoring operation will continue indefinitely given a properly operating network connection with good signal integrity. If the link state monitor does not recognize at least 6 unscrambled idle symbols within 722 us period, the de-scrambler will be forced out of the current state of synchronization and reset in order to re-acquire synchronization.
Symbol Alignment The symbol alignment circuit in the ADM7001 determines code word alignment by recognizing the /J/K delimiter pair. This circuit operates on unaligned data from the descrambler. Once the /J/K symbol pair (11000 10001) is detected, subsequent data is
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ADM7001 aligned on a fixed boundary.
Function Description
Symbol Decoding The symbol decoder functions as a look-up table that translates incoming 5B symbols into 4B nibbles as shown in Table 3-1. The symbol decoder first detects the /J/K symbol pair preceded by idle symbols and replaces the symbol with MAC preamble. All subsequent 5B symbols are converted to the corresponding 4B nibbles for the duration of the entire packet. This conversion ceases upon the detection of the /T/R symbol pair denoting the end of stream delimiter (ESD). The translated data is presented on the internal RXD[3:0] signal lines with RXD[0] represents the least significant bit of the translated nibble.
PCS code-group [4:0] 11110 01001 10100 10101 01010 01011 01110 01111 10010 10011 10110 10111 11010 11011 11100 11101 11111 11000 Name 0 1 2 3 4 5 6 7 8 9 A B C D E F I J MII (TXD/RXD) <3:0> 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Undefined 0101 Interpretation Data 0 Data 1 Data 2 Data 3 Data 4 Data 5 Data 6 Data 7 Data 8 Data 9 Data A Data B Data C Data D Data E Data F IDLE used as inter-stream fill code Start-of-Stream Delimiter, Part 1 of 2; always used in pairs with K Start-of-Stream Delimiter, Part 2 of 2; always used in pairs with J Start-of-Stream Delimiter, Part 1 of 2; always used in pairs with R Start-of-Stream Delimiter, Part 2 of 2; always used in pairs with T Transmit Error; used to force signaling errors
10001
K
0101
01101
T
Undefined
0111
R
Undefined
00100
H
Undefined
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ADM7001
PCS code-group [4:0] 00000 00001 00010 00011 00101 00110 01000 01100 10000 11001 MII (TXD/RXD) <3:0> Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined
Function Description
Name V V V V V V V V V V
Interpretation Invalid code Invalid code Invalid code Invalid code Invalid code Invalid code Invalid code Invalid code Invalid code Invalid code
Table 3-1 Look-up Table for translating 5B Symbols into 4B Nibbles.
Valid Data Signal The valid data signal (RXDV) indicates that recovered and decoded nibbles are being presented on the internal RXD[3:0] synchronous to receive clock, RXCLK. RXDV is asserted when the first nibble of translated /J/K is ready for transfer over the internal MII. It remains active until either the /T/R delimiter is recognized, link test indicates failure, or no signal is detected. On any of these conditions, RXDV is de-asserted. Receive Errors The RXER signal is used to communicate receiver error conditions. While the receiver is in a state of holding RXDV asserted, the RXER will be asserted for each code word that does not map to a valid code-group. 100Base-X Link Monitor The 100Base-X link monitor function allows the receiver to ensure that reliable data is being received. Without reliable data reception, the link monitor will halt both transmit and receive operations until such time that a valid link is detected.
The ADM7001 performs the link integrity test as outlined in IEEE 100Base-X (Clause 24) link monitor state diagram. The link status is multiplexed with 10 Mbps link status to form the reportable link status bit in serial management register 1h, and driven to the LNKACT pin. When persistent signal energy is detected on the network, the logic moves into a LinkReady state after approximately 500 us, and waits for an enable from the auto negotiation module. When receive, the link-up state is entered, and the transmission and reception logic blocks become active. Should auto negotiation be disabled, the link integrity logic moves immediately to the link-up state after entering the link-ready state.
Carrier Sense
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Function Description Carrier sense (CRS) for 100 Mbps operation is asserted upon the detection of two noncontiguous zeros occurring within any 10-bit boundary of the received data stream. The carrier sense function is independent of symbol alignment. In switch mode, CRS is asserted during either packet transmission or reception. For repeater mode, CRS is asserted only during packet reception. When the idle symbol pair is detected in the received data stream, CRS is disserted. In repeater mode, CRS is only asserted due to receive activity. CRS is intended to encapsulate RXDV.
Bad SSD Detection A bad start of stream delimiter (Bad SSD) is an error condition that occurs in the 100Base-X receiver if carrier is detected (CRS asserted) and a valid /J/K set of codegroup (SSD) is not received.
If this condition is detected, then the ADM7001 will assert RXER and present RXD[3:0] = 1110 to the internal MII for the cycles hat correspond to received 5B code-groups until at least two idle code-groups are detected. Once at least two idle code groups are detected, RXER and CRS become de-asserted.
Far-End Fault Auto negotiation provides a mechanism for transferring information from the Local Station to the link Partner that a remote fault has occurred for 100Base-TX. As auto negotiation is not currently specified for operation over fiber, the far end fault indication function (FEFI) provides this capability for 100Base-FX applications.
A remote fault is an error in the link that one station can detect while the other cannot. An example of this is a disconnected wire at a station's transmitter. This station will be receiving valid data and detect that the link is good via the link integrity monitor, but will not be able to detect that its transmission is not propagating to the other station. A 100Base-FX station that detects such a remote fault may modify its transmitted idle stream from all ones to a group of 84 ones followed by a single 0. This is referred to as the FEFI idle pattern. The FEFI function is controlled by bit 3 of register 11h. It is initialized to 1 (encoded) if the SELFX pin is at logic high level during power on reset. If the FEFI function is enabled the ADM7001 will halt all current operations and transmit the FEFI idle pattern when FOSD signal is de-asserted following a good link indication from the link integrity monitor. FOSD signal is generated internally from the internal signal detect circuit. Transmission of the FEFI idle pattern will continue until link up signal is asserted. If three or more FEFI idle patterns are detected by the ADM7001, then bit 4 of the Basic mode status register (address 1h) is set to one until read by management. Additionally, upon detection of far end fault, all receive and transmit MII activity is disabled/ignored.
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3.1.3
Function Description
100Base-TX Transmitter ADM7001 implements a TP-PMD compliant transceiver for 100Base-TX operation. The differential transmit driver is shared by the 10Base-T and 100Base-TX subsystems. This arrangement results in one device that uses the same external magnetics for both the 10Base-T and the 100Base-TX transmission with simple RC component connections. The individually wave-shaped 10Base-T and 100Base-TX transmit signals are multiplexed in the transmission output driver selection.
ADM7001 100Base-TX transmission driver implements MLT-3 translation and waveshaping functions. The rise/fall time of the output signal is closely controlled to conform to the target range specified in the ANSI TP-PMD standard.
3.1.4 100Base-FX Receiver Signal is received through PECL receiver inputs from fiber transceiver, and directly passed to clock recovery circuit for data/clock recovery. Scrambler/de-scrambler is bypassed in 100Base-FX. Automatic "Signal_Detect" Function Block When DIS_ANASDEN_N in register 18 is set to 0, ADM7001 doesn't support SDP detection in fiber mode, which is used to connect to fiber transceiver to indicate there is signal on the fiber. Instead, ADM7001 use the data on RXP/RXN to detect consecutive 65 "1" on the receive data (Recovered from RXP/RXN) to determine whether "Signal" is detected or not. When the detect condition is true (Consecutive 65 bits "1"), internal signal detect signal will be asserted to inform receive relative blocks to be ready for coming receive activities. 3.1.5 100Base-FX Transmitter In 100Base FX transmit, the serial data stream is driven out as NRZI PECL signals, which enters fiber transceiver in differential-pairs form. Fiber transceiver should be available working at 3.3V environment. 3.1.6 10Base-T Module The 10Base-T Transceiver Module is IEEE 802.3 compliant. It includes the receiver, transmitter, collision, heartbeat, loop-back, jabber, wave-shaper, and link integrity functions, as defined in the standard. Figure 5 provides an overview for the 10Base-T module.
The ADM7001 10Base-T module is comprised of the following functional blocks: * Manchester encoder and decoder * Collision detector * Link test function * Transmit driver and receiver * Serial and parallel interface * Jabber and SQE test functions * Polarity detection and correction
3.1.7 Operation Modes The ADM7001 10Base-T module is capable of operating in either half-duplex mode or full-duplex mode. In half-duplex mode, the ADM7001 functions as an IEEE 802.3
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Function Description compliant transceiver with fully integrated filtering. The COL signal is asserted during collisions or jabber events, and the CRS signal is asserted during transmit and receive. In full duplex mode the ADM7001 can simultaneously transmit and receive data.
3.1.8
Manchester Encoder/Decoder Data encoding and transmission begins when the transmission enable input (TXEN) goes high and continues as long as the transceiver is in good link state. Transmission ends when the transmission enable input goes low. The last transition occurs at the center of the bit cell if the last bit is a 1, or at the boundary of the bit cell if the last bit is 0.
A differential input receiver circuit accomplishes decoding and a phase-locked loop that separate the Manchester-encoded data stream into clock signals and NRZ data. The decoder detects the end of a frame when no more mid-bit transitions are detected. Within one and half bit times after the last bit, carrier sense is disserted.
3.1.9 Transmit Driver and Receiver The ADM7001 integrates the entire required signal conditioning functions in its 10BaseT block such that external filters are not required. Only one isolation transformer and impedance matching resistors are needed for the 10Base-T transmit and receive interface. The internal transmit filtering ensures that all the harmonics in the transmission signal are attenuated properly.
3.1.10 Smart Squelch The smart squelch circuit is responsible for determining when valid data is present on the differential receives. The ADM7001 implements an intelligent receive squelch on the RXP/RXN differential inputs to ensure that impulse noise on the receive inputs will not be mistaken for a valid signal. The squelch circuitry employs a combination of amplitude and timing measurements (as specified in the IEEE 802.3 10Base-T standard) to determine the validity of data on the twisted-pair inputs.
The "analog squelch circuit" checks the signal at the start of the packet and any pulses not exceeding the squelch level (either positive or negative, depending upon polarity) will be rejected. Once this first squelch level is overcome correctly, the opposite squelch level must then be exceeded within 150ns. Finally, the signal must exceed the original squelch level within an additional 150ns to ensure that the input waveform will not be rejected. Only after all these conditions have been satisfied will a control signal be generated to indicate to the remainder of the circuitry that valid data is present.
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Function Description
Figure 3-2 10Base-T Block Diagram and Data Path
Valid data is considered to be present until the squelch level has not been generated for a time longer than 200 ns, indicating end of packet. Once good data has been detected, the squelch levels are reduced to minimize the effect of noise, causing premature end-ofpacket detection. The receive squelch threshold level can be lowered for use in longer cable applications. This is achieved by setting bit 7 of register address 10h.
3.1.11 Carrier Sense Carrier Sense (CRS) is asserted due to receive activity once valid data is detected via the smart squelch function. For 10 Mbps half duplex operation, CRS is asserted during either packet transmission or reception. For 10 Mbps full duplex and repeater mode operations, the CRS is asserted only due to receive activity.85 3.1.12 Collision Detection Collision is detected internal to the MAC, which is generated by an AND function of TXEN and RXDV derived from internal timing recovery circuitry. Note should be taken that due to TXEN and RXDV are asynchronous to each other, COL signal outputted by ADM7001 is irrelevant to either TXCLK or RXCLK. 3.1.13 Jabber Function The jabber function monitors the ADM7001 output and disables the transmitter if it attempts to transmit a longer than legal sized packet. If TXEN is high for greater than 24ms, the 10Base-T transmitter will be disabled. Once disabled by the jabber function, the transmitter stays disabled for the entire time that the TXEN signal is asserted. This signal has to be de-asserted for approximately 408 ms (The un-jab time) before the jabber
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Function Description function re-enables the transmit outputs. The jabber function can be disabled by programming bit 0 of register address 10h to high.
3.1.14 Link Test Function A link pulse is used to check the integrity of the connection with the remote end. If valid link pulses are not received, the link detector disables the 10Base-T twisted-pair transmitter, receiver, and collision detection functions. The link pulse generator produces pulses as defined in IEEE 802.3 10Base-T standard. Each link pulse is nominally 100ns in duration and is transmitted every 16 ms, in the absence of transmit data. Setting bit 10 of register 10h to high can disable link pulse check function. 3.1.15 Automatic Link Polarity Detection ADM7001's 10Base-T transceiver module incorporates an "automatic link polarity detection circuit". The inverted polarity is determined when seven consecutive link pulses of inverted polarity or three consecutive packets are received with inverted end-ofpacket pulses. If the input polarity is reversed, the error condition will be automatically corrected and reported in bit 13 of register 11h. 3.1.16 Clock Synthesizer The ADM7001 implements a clock synthesizer that generates all the reference clocks needed from a single external frequency source. The clock source must be a TTL level signal at 25 MHz +/- 50ppm. 3.1.17 Auto Negotiation The Auto Negotiation function provides a mechanism for exchanging configuration information between two ends of a link segment and automatically selecting the highest performance mode of operation supported by both devices. Fast Link Pulse (FLP) Bursts provide the signaling used to communicate auto negotiation abilities between two devices at each end of a link segment. For further detail regarding auto negotiation, refer to Clause 28 of the IEEE 802.3u specification. The ADM7001 supports four different Ethernet protocols, so the inclusion of auto negotiation ensures that the highest performance protocol will be selected based on the ability of the link partner.
The auto negotiation function within the ADM7001 can be controlled either by internal register access or by the use of configuration pins are sampled. If disabled, auto negotiation will not occur until software enables bit 12 in register 0. If auto negotiation is enabled, the negotiation process will commence immediately. When auto negotiation is enabled, the ADM7001 transmits the abilities programmed into the auto negotiation advertisement register at address 04h via FLP bursts. Any combination of 10 Mbps, 100 Mbps, half duplex and full duplex modes may be selected. Auto negotiation controls the exchange of configuration information. Upon successfully auto negotiation, the abilities reported by the link partner are stored in the auto negotiation link partner ability register at address 05h. Infineon ADMtek Co Ltd 3-10
ADM7001
Function Description
The contents of the "auto negotiation link partner ability register" are used to automatically configure to the highest performance protocol between the local and farend nodes. Software can determine which mode has been configured by auto negotiation by comparing the contents of register 04h and 05h and then selecting the technology whose bit is set in both registers of highest priority relative to the following list. 1. 2. 3. 4. 100Base-TX full duplex (highest priority) 100Base-TX half duplex 10Base-T full duplex 10Base-T half duplex (lowest priority)
The basic mode control register at address 0h provides control of enabling, disabling, and restarting of the auto negotiation function. When auto negotiation is disabled, the speed selection bit (bit 13) controls switching between 10 Mbps or 100 Mbps operation, while the duplex mode bit (bit 8) controls switching between full duplex operation and half duplex operation. The speed selection and duplex mode bits have no effect on the mode of operation when the auto negotiation enable bit (bit 12) is set. The basic mode status register (BMSR) at address 1h indicates the set of available abilities for technology types (bit 15 to bit 11), auto negotiation ability (bit 3), and extended register capability (bit 0). These bits are hardwired to indicate the full functionality of the ADM7001. The BMSR also provides status on : 1.Whether auto negotiation is complete (bit 5) 2.Whether the Link Partner is advertising that a remote fault has occurred (bit 4) 3.Whether a valid link has been established (bit 2) The auto negotiation advertisement register at address 4h indicates the auto negotiation abilities to be advertised by the ADM7001. All available abilities are transmitted by default, but writing to this register or configuring external pins can suppress any ability. The auto negotiation link partner ability register at address 05h indicates the abilities of the Link Partner as indicated by auto negotiation communication. The contents of this register are considered valid when the auto negotiation complete bits (bit 5, register address 1h and bit 4, register 17h) is set.
3.1.18 Auto Negotiation and Speed Configuration The twelve sets of four pins listed in Table 3-2 Channel Configuration. Configure the speed capability of each channel of ADM7001. The logic state of these pins is latched into the advertisement register (register address 4h) for auto negotiation purpose. These pins are also used for evaluating the default value in the base mode control register (register 0h) according to Table 3-2 Channel Configuration.
3.2
MAC Interface
The ADM7001 interfaces to 10/100 Media Access Controllers (MAC) via the RMII, MII, or GPSI Interface.
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ADM7001
Function Description
3.2.1
Reduced Media Independent Interface (RMII) The reduced media Independent interface (RMII) is compliant to the RMII consortium's RMII Rev. 1.2 specification. The XI/OSCI pin that supplies the 50 MHz reference clock to the ADM7001 is used as the RMII REFCLK signal. All RMII signals with the exception of the assertion of CRSDV_P are synchronous to REFCLK.
Figure 3-3 RMII Signal Diagram
3.2.2
Receive Path for 100M Figure 3-4 shows the relationship among REFCLK, CRSDV, RXD and RXER while receiving a valid packet. Carrier sense is detected, which causes CRSDV to assert asynchronously to REFCLK. The received data is then placed into the FIFO for resynchronization. After a minimum of 12 bits are placed into the FIFO, the received data is presented onto RXD[1:0] synchronously to REFCLK. Note that while the FIFO is filling up RXD[1:0] is set to 00 until the first received di-bit of preamble (01) is presented onto RXD[1:0]. When carrier sense is de-asserted at the end of a packet, CRSDV is deasserted when the first di-bit of a nibble is presented onto RXD[1:0] synchronously to REFCLK. If there is still data in the FIFO that has not yet been presented onto RXD[1:0], then on the second di-bit of a nibble, CRSDV reasserts. This pattern of assertion and de-assertion continues until all received data in the FIFO has been presented onto RXD[1:0]. RXER is inactive for the duration of the received valid packet.
Figure 3-5 shows the relationship among REFCLK, CRSDV and RXD[1:0] during a received false carrier event. CRSDV is asserted asynchronously to REFCLK as in the valid receive case shown in . However, once false carrier is detected, RXD[1:0] is changed to (10) (11) (Value 1110 in MII) and RXER is asserted. Both RXD[1:0] and RXER transition synchronously to REFCLK. After carrier sense is de-asserted, CRSDV is de-asserted synchronously to REFCLK.
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ADM7001
Function Description
REFCLK CRSDV RXD RXER
Carrier Sense Detected Preamble SFD Carrier Deasserted Data 00 00 00 00 00 00 01 01 01 01 01 11 Data Data Data Data Data Data Data Data Data 00 00 00
Figure 3-4 RMII Reception Without Error
Figure 3-5 RMII Reception with False Carrier (100M Only)
A receive symbol error event is shown in figure 3-6. The packet with the symbol error is treated as if it were a valid packet with the exception that all di-bits are substituted with the (01) pattern.
Figure 3-6 RMII Reception with Symbol Error
3.2.3
Receive Path for 10M
Figure 3-7 10M RMII Receive Diagram
In 10M Mode, RXER will maintain low all the time due to False Carrier and symbol error is not supported by 10M Mode. Different from 100M mode, RXD and CRSDV can Infineon ADMtek Co Ltd 3-13
ADM7001
Function Description transition once per 10 REFCLK cycles. After carrier sense is de-asserted yet the FIFO data is not fully presented onto RXD, the CRSDV de-assertion and re-assertion also follows this rule.
3.2.4
Transmit Path for 100M
Figure 3-8 100M RMII Transmit Diagram
Figure 3-8 shows the relationship among REFCLK, TXEN and TXD[1:0] during a transmit event. TXEN and TXD[1:0] are synchronous to REFCLK. When TXEN is asserted, it indicates that TXD[1:0] contains valid data to be transmitted. When TXEN is de-asserted, value on TXD[1:0] should be ignored. If an odd number of di-bits are presented onto TXD[1:0] and TXEN, the final di-bit will be discarded by ADM7001.
3.2.5 Transmit Path for 10M In 10MBSE-T mode, each di-bit must be repeated 10 times by the MAC, TXEN and TXD[1:0] should be synchronous to REFCLK. When TXEN is asserted, it indicates that data on TXD[1:0] is valid for transmission.
Figure 3-9 10M RMII Transmit Diagram
In 10BASE-T mode, it is possible that the number of preamble bits and the number of frame bits received are not integer nibbles. The preamble is always padded up such that the SFD appears on the RMII aligned to the nibble boundary. Extra bits at the end of the frame that do not complete a nibble are truncated by ADM7001. Figure 3 9 shows the timing diagram for 10M Transmission.
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ADM7001
Table 3-2 Channel Configuration
Function Description
3.2.6 Media Independent Interface (MII) Signal Diagram for MII interface is shown in Figure 3-10.
ANEN
1 1 1 1 0 0 0 0
Recommend Value SPD100 DUPFUL 1 1 1 0 0 1 0 0 1 1 1 0 0 1 0 0
Auto Negotiation Enable Disable
Capability 100 Full 100 Half 10 Full
10 Half
Figure 3-10 MII Signal Diagram
3.2.7
Receive Path for MII Figure 3-11 shows the relationship among RXCLK, RXDV, RXD and CRS during a reception of valid packet. Carrier sense is detected and asserted asynchronously to RXCLK by ADM7001. When ADM7001 detects there is valid data, RXDV and the
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ADM7001
Function Description received data is presented onto RXD[3:0] synchronously to RX_CLK. Whenever received data is not valid anymore, RXDV will be de-asserted by ADM7001 and "0" will be put on RXD[3:0].
Figure 3-11 MII Receive Without Error
Figure 3-12 shows the relationship among RXCLK, RXDV and RXD[3:0] during a received false carrier event. CRS is asserted asynchronously to RXCLK as in the valid receive case shown in Figure 3-13. However, once false carrier is detected, RXD[3:0] is changed to (1110) and RXER is asserted. Both RXD[3:0] and RXER transition synchronously to RXCLK.
RXCLK CRS RXDV RXD[3:0]
0 0 0 0 0 0 5 E E E E E E E E E E E 00 00 00
RXER
Carrier Sense Detected False Carrier Detected False Carrier Carrier Deasserted
Figure 3-12 MII Receive With False Carrier
A receive symbol error event is shown in Figure 3-13. The packet with the symbol error is treated as if it were a valid packet with the exception that all bits are substituted with the (0101) pattern. RXER will keep low in 10M Operation.
Figure 3-13 MII Receive With Symbol Error (100M Only)
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ADM7001
Function Description
3.2.8
Transmit Path For MII Figure 3 14 shows the relationship among TXCLK, TXEN and TXD[3:0] during a transmit event. TXEN and TXD[3:0] are synchronous to TXCLK, which is generated by MAC. TXCLK is running at 25M in 100M mode and 2.5M in 10M mode. When TXEN is asserted, it indicates that TXD[3:0] contains valid data to be transmitted. When TXEN is de-asserted, value on TXD[1:0] should be ignored.
Figure 3-14 MII Transmission
When ADM7001 operates in half duplex mode, either 10M or 100M, it will assert COL signal whenever it detects there is collision on the medium. Figure 3-15 shows the timing diagram for MII Collision.
Figure 3-15 MII Transmit with Collision (Half Duplex Only)
3.2.9
General Purpose Serial Interface (GPSI) Signal Diagram for MII interface is shown in Figure 3-16.
Figure 3-16 GPSI Signal Diagram
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ADM7001
Function Description
3.2.10 Receive Path for GPSI Figure 3-17 shows the relationship among RXCLK, RXD and CRS during a receive of valid packet. Carrier sense is detected and asserted asynchronously to RXCLK by ADM7001. When ADM7001 detects there is valid data, received data is presented onto RXD synchronously to RXCLK. Whenever received data is not valid anymore, CRS will be de-asserted by ADM7001 and "0" will be put on RXD.
Figure 3-17 GPSI Receive Diagram
3.2.11 Transmit Path for GPSI Figure 3-18 shows the relationship among TXCLK, TXEN and TXD during a transmit event. TXEN and TXD are synchronous to TXCLK, which is generated by MAC. TXCLK is running at 10M in 10M mode. When TXEN is asserted, it indicates that TXD contains valid data to be transmitted. When TXEN is de-asserted, value on TXD should be ignored.
Figure 3-18 GPSI Transmit Diagram
3.3
LED Display
Register 19 is used for different mode led display. ADM7001 provides power on LED self test to minimize and ease the system test cost. All LEDs will be Off during power on reset (Output value same as recommend value on LED pins). After power on reset, all internal parallel LEDs will be On for 2 seconds to ease manufacture overhead There are three types of LED supported by ADM7001 internally. The first is LNKACT, which represents the status of Link and Transmit/Receive Activity; the second is LDSPD, which indicates the speed status and the last is DUPCOL, which shows pure duplex status in full duplex and duplex/collision combined status in half duplex. All these three LED can be controlled by Register 19 to change display contents. After LED self test, Table 3-4, 3-5 and 3-6 show the On/Off polarity according to different recommended value setting for LDSPD, DUPCOL and LNKACT. When the
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ADM7001
Function Description recommend value is high, ADM7001 will drive LED LOW; ADM7001 will drive the LED HIGH when the recommend value is low, instead.
SPEED 10M 100M LINK FAIL Table 3-3 Speed LED Display LDSPD 0 1 1
DUPLEX LINK UP LINK FAIL
DUPCOL HALF Blink (HIGH) When Collision HIGH All the Time Table 3-4 Duplex LED Display Link/Activity Link LOW HIGH All the Time Table 3-5 Activity/Link LED Display Activity Blink (HIGH) When RX/TX HIGH All the Time FULL LOW All the Time HIGH All the Time
SPEED LINK UP LINK FAIL
Besides duplex, speed, link and activity status, ADM7001 also provides cable information that can be shown on LEDs when register 19 is programmed to distance LED display (see Table 3-6).
LNKACT 1 1 0 1
DUPCOL LEDSPD 1 0 0 0 0 0 1 1 Table 3-6 Cable Distance LED Display
Cable Distance 0 to 40 meters 40 to 80 meters 80 to 120 meters Reserved
3.4
Management Register Access
The SMI consists of two pins, management data clock (MDC) and management data input/output (MDIO). The ADM7001 is designed to support an MDC frequency specified in the IEEE specification of up to 2.5 MHz. The MDIO line is bi-directional and may be shared by up to 32 devices. The MDIO pin requires a 1.5 K pull-up which, during idle and turnaround periods, will pull MDIO to a logic one state. Each MII management data frame is 64 bits long. The first 32 bits are preamble consisting of 32 contiguous logic one bits on MDIO and 32
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ADM7001
Function Description corresponding cycles on MDC. Following preamble is the start-of-frame field indicated by a <01> pattern. The next field signals the operation code (OP) : <10> indicates read from MII management register operation, and <01> indicates write to MII management register operation. The next two fields are PHY device address and MII management register address. Both of them are 5 bits wide and the most significant bit is transferred first. During Read operation, a 2-bit turn around (TA) time spacing between the register address field and data field is provided for the MDIO to avoid contention. Following the turnaround time, a 16-bit data stream is read from or written into the MII management registers of the ADM7001.
3.4.1
Preamble Suppression The ADM7001 supports a preamble suppression mode as indicated by an 1 in bit 6 of the basic mode status register (Register 1h). If the station management entity (i.e. MAC or other management controller) determines that all PHYs in the system support preamble suppression by reading a 1 in this bit, then the station management entity needs not generate preamble for each management transaction. The ADM7001 requires a single initialization sequence of 32 bits of preamble following powerup/hardware reset. This requirement is generally met by pulling-up the resistor of MDIO. While the ADM7001 will respond to management accesses without preamble, a minimum of one idle bit between management transactions is required as specified in IEEE 802.3u.
When ADM7001 detects that there is physical address match, then it will enable Read/Write capability for external access. When neither physical address nor register address is matched, then ADM7001 will tri-state the MDIO pin.
Figure 3-19 SMI Read Operation
3.4.2
Reset Operation The ADM7001 can be reset either by hardware or software. A hardware reset is accomplished by applying a negative pulse, with duration of at least 200 ms to the RC pin of the ADM7001 during normal operation to guarantee internal Power On Reset Circuit is reset well. Setting the reset bit in the Basic Mode Control activates software reset Register (bit 15, register 0h). This bit is self-clearing and, when set, will return a value of 1 until the software reset operation has completed, please note that internal SRAM will not be reset during software reset.
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ADM7001
Function Description
Figure 3-20 SMI Write Operation
Hardware reset operation samples the pins and initializes all registers to their default values. This process includes re-evaluation of all hardware configurable registers. A software reset will reset an individual PHY and it does not latch the external pins nor reset the registers to their respective default value. Logic levels on several I/O pins are detected during a hardware reset to determine the initial functionality of ADM7001. Some of these pins are used as output ports after reset operation. Care must be taken to ensure that the configuration setup will not interfere with normal operation. Dedicated configuration pins can be tied to VCC or Ground directly. Configuration pins multiplexed with logic level output functions should be either weakly pulled up or weakly pulled down through resistors.
3.5
Power Management
An analog block is designed for carrier sense detecting. When there is no carrier sense presented on medium (cable not attached), then "SIGNAL DETECT" will not be ON. Whenever cable is attached to ADM7001 and the voltage threshold is above +/- 50mV, then SD will be asserted HIGH to indicate that there is cable attached to ADM7001. All internal blocks except Management block will be disabled (reset) before SD is asserted. When SD is asserted, internal Auto Negotiation block will be turned on and the 10M transmit driver will also be turned on for auto negotiation process. Auto negotiation will issue control signals to control 10M receive and 100M A/D block according to different state in arbitration block diagram. During auto negotiation, all digital blocks except management and link monitor blocks will be disabled to reduce power consumption. Whenever operating speed is determined (Either auto negotiation is On or Off), the nonactive speed relative circuit will be disabled all the time to save more power. For example, when corresponding port is operating on 10M, then 100M relative blocks will be disabled and 10M relative blocks will be disabled whenever corresponding port is in 100M mode. Auto negotiation block will be reset when SD signal goes from high to low. See figure 3-21 for the state diagram for this algorithm.
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ADM7001
Function Description
Figure 3-21 Medium Detect Power Management Flow Chart
Another way to reduce instant power is to separate the LED display period. All 4 LEDs will be divided into 4 time frame and each time frame occupies 1 us. One and only one LED will be driven at each time frame to reduce instant current consumed from LED.
3.6
Voltage Regulator
ADM7001 requires two different levels, 3.3V and 2.5V, of voltage supply to provide the power to different parts of circuitry inside the chip. ADM7001 has a build-in voltage regulator circuitry to generate the 2.5V voltage (VCC25OUT) from 3.3V power source (VCC3IN). External Application Circuitry is shown in 3-22.
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ADM7001
3.3V C1 10uF C2 0.1uF C3 0.01uF
48 PHYAD4/RXD0 47 46 44 45 43 42 41 39 40 38 37
Function Description
2.5V
C4
C5
C6
PYYAD3/RXD1
PHYAD2/RXD2
MDC PHYAD1/RXD3
MDIO
RESET_N
VCC33IN
XO XI
TEST1
GNDIK
0.1uF
22uF
1uF
2.5V C7 0.1uF C8 0.01uF C9 0.1uF C12 0.01uF
1 2 3 4 5 6 7 8 9 10 11 12 VCCO_25 GNDIK RXDV/CRSDV/DIS_AMDIX RMII_EN/RX_CLK ISOLATE/RXER GNDO VCCIK_25 TXER TXCLK TXEN TXD0 TXD1 VCC25OUT(CORE) TXP TXN GNDPLL VCCPLL_25 RTX TEST0 GNDTR SD/FXEN RXP RXN VCCA_25 36 35 34 33 32 31 30 29 28 27 26 25
2.5V
ADM7001 QFP 48
CONV/REPEATER/CRS FEFI_EN/LNKACT ANEN/COLLED DUPFUL/DUPLED
VCCPLL C10
C11
1nF
22uF
2.5V
SPD100/SPDLED
PHYAD0/INTR
PWRDOWN_N
C13
C14
COL/GPSI
VCCO_2.5 GNDO
2.5V C15 1uF C16 0.01uF
Figure 3-22 Power and Ground Filtering
Note: Place all capacitors as close as possible to each power pin.
TXD2
TXD3
0.1uF
0.01uF
13
14
15
16
18 17
20 19
21
22
24 23
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ADM7001
Register Description
Chapter 4
Register Description
Note: Please refer to section `1.5.2 Register Type Descriptions' for an explanation of pin abbreviations.
4.1
Register Mapping
Address 0h 1h 2h - 3h 4h 5h 6h 7h - Fh 10h 11h 12h 13h 14h 16h 17h 18h 19h 1Dh 1Eh 1Fh Register Name
Control Register Status Register PHY Identifier Register Auto Negotiation Advertisement Register Auto Negotiation Link Partner Ability Register Auto Negotiation Expansion Register Reserved PHY Control Register PHY 10M Configuration Register PHY 100M Configuration Register LED Configuration Register Interrupt Enable Register PHY Generic Status Register PHY Specific Status Register Recommend Value Storage Register Global Interrupt Status Register Receive Error Counter Reserved Chip ID Register
Default 3000 7849 002E_CC62 01E1 01E1 0000 Reserved 1000 0008 0022 0A34 03FF 0000 0060 0000 0000 0000 1000 8125
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ADM7001
Register Description
4.2
4.2.1
15
RST R/W
Register Bit Mapping
Register #0h -- Control Register
14
LPBK R/W
13
SPD_L R/W
12
ANEN R/W
11
PDN R/W
10
ISO R/W
9
RSTAR R/W
8
7
6
5
0 RO
4
0 RO
3
0 RO
2
0 RO
1
0 RO
0
0 RO
DPLX COLTST SPDMSB PIN R/W R/W
4.2.2
15
CAPT4 RO
Register #1h - Status Register
14 13 12 11
THALF RO
10
CAPT2 RO
9
0 RO
8
0 RO
7
0 RO
6
5
4
3
ANEN RO
2
LINK RO
1
JAB RO
0
EXTCAP RO
TXFUL TXHALF TFUL RO RO RO
MFSUP ANCOMP RMFLT RO RO RO
4.2.3
15
ID15 RO
Register #2h - PHY ID Register (002E)
14
ID14 RO
13
ID13 RO
12
ID12 RO
11
ID11 RO
10
ID10 RO
9
ID9 RO
8
ID8 RO
7
ID7 RO
6
ID6 RO
5
ID5 RO
4
ID4 RO
3
ID3 RO
2
ID2 RO
1
ID1 RO
0
ID0 RO
4.2.4 Register #3h - PHY ID Register (CC62)
15
ID5 RO
14
ID4 RO
13
ID3 RO
12
ID2 RO
11
ID1 RO
10
ID0 RO
9
MOD5 RO
8
MOD4 RO
7
MOD3 RO
6
MOD2 RO
5
MOD1
4
MOD0 RO
3
REV3 RO
2
REV2 RO
1
REV1 RO
0
REV0 RO
RO
4.2.5
15
NPAGE R/W
Register #4h - Advertisement Register
14
0 RO
13
RF R/W
12
0 RO
11
10
9
T4 RO
8
7
6
5
HDX10 R/W
4
0 RO
3
0 RO
2
0 RO
1
0 RO
0
1 RO
ASM_DIR PAUSE
FDX100 HDX100 FDX10 R/W R/W R/W
R/W
R/W
4.2.6
15
NPAGE RO
Register #5h - Link Partner Ability Register
14
ACK RO
13
RF RO
12
0 RO
11
10
9
8
7
6
5
4
0 RO
3
0 RO
2
0 RO
1
0 RO
0
1 RO
LP_DIR LP_PAU LP_T4 LP_FDX LP_HDX LP_F10 LP_H10 RO RO RO RO RO RO RO
4.2.7 Register #6h - Auto Negotiation Expansion Register
15
0 RO
14
0 RO
13
0 RO
12
0 RO
11
0 RO
10
0 RO
9
0 RO
8
0 RO
7
0 RO
6
0 RO
5
0 RO
4
3
2
1
0
PDFLT LPNPAB NPABLE PGRCV LPANAB RO RO RO RO RO
4.2.8 Register #7h - # Fh Reserved 4.2.9 Register #10h - PHY Configuration Register
15
IFSEL1 RO
14
13
12
11
0 RO
10
0 RO
9
8
7
0 RO
6
0 RO
5
0 RO
4
XOVEN R/W
3
0 R/W
2
0 R/W
1
0 RO
0
DISPMG R/W
IFSEL0 LBKMD1 LBKMD0 RO R/W R/W
FLTLED CONV R/W R/W
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ADM7001
4.2.10 Register #11h - 10M Configuration Register
15
0 RO
Register Description
14
SERIAL RO
13
1
12
0
11
0
10
INTCHKEN
9
1
8
1
7
0
6
1
5
0
4
3
2
1
NTH R/W
0
FGDLNK R/W
APDIS ENRJAB DISTJAB R/W R/W R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
4.2.11 Register #12h - 100M Configuration Register
15
0 RO
14
0 RO
13
0 RO
12
0 RO
11
0 R/W
10
0 R/W
9
0 R/W
8
0 R/W
7
SELFX R/W
6
0
5
1
4
3
2
1
0
0 RO
DISSCR ENFEFI R/W R/W
DIS_CABL INTR_AC EN_LED
TIVE R/W
R/W
R/W
R/W
4.2.12 Register #13h - LED Configuration Register
15
0 RO
14
0 RO
13
Reserved
12
Reserved
11
LNKC3 R/W
10
LNKC2 R/W
9
LNKC1 R/W
8
LNKC0 R/W
7
COLC3 R/W
6
COLC2 R/W
5
COLC1 R/W
4
COLC0 R/W
3
SPDC3 R/W
2
SPDC2 R/W
1
SPDC1 R/W
0
SPDC0 R/W
R/W
R/W
4.2.13 Register #14h - Interrupt Enable Register
15
0 RO
14
0 RO
13
0 RO
12
0 RO
11
0 RO
10
0 RO
9
8
7
6
5
4
3
FCAR R/W
2
1
0
XOVCHG SPDCHG DUPCHG PGRCHG LNKCHG SYMERR
FOURUN TJABINT RJABINT
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
4.2.14 Register #16h - PHY Generic Status Register
15
0 RO
14
0 RO
13
Reserved
12
Reserved
11
Reserved
10
MD RO
9
FXEN RO
8
7
6
5
4
3
2
1
0
XOVER CBLEN7 CBLEN6 CBLEN5 CBLEN4 CBLEN3 CBLEN2 CBLEN1 CBLEN0 RO RO RO RO RO RO RO RO RO
RO
RO
RO
4.2.15 Register #17h - PHY Specific Status Register
15
0 RO
14
0 RO
13
0 RO
12
0 RO
11
JABRX RO
10
9
8
7
6
5
4
LINK RO
3
2
1
0
JABTX POLAR PAUOUT PAUIN DUPLEX SPEED RO RO RO RO RO RO
RECPAU RECDUP RECSPD RECAN RO RO RO RO
4.2.16 Register #18h - Recommend Value Storage Register
15
0 RO
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RECAN SELFX REC100 RECFUL PAUREC DISFEFI XOVEN XOVER RO RO RO RO RO RO RO RO
RMII_SMII REPEATER
PHYA4 PHYA3 PHYA2 PHYA1 PHYA0 RO RO RO RO RO
RO
RO
4.2.17 Register #19h - Interrupt Status Register
15
0 RO
14
0 RO
13
0 RO
12
0 RO
11
0 RO
10
0 RO
9
8
7
6
5
4
3
FCAR RO
2
1
0
XOVCHG SPDCHG DUPCHG PGRCHG LNKCHG SYMERR
FOURUN TJABINT RJABINT
RO
RO
RO
RO
RO
RO
RO
RO
RO
4.2.18 Register #1dh - Receive Error Counter
15
ERB15 RO
14
ERB14 RO
13
ERB13 RO
12
ERB12 RO
11
ERB11 RO
10
ERB10 RO
9
ERB9 RO
8
ERB8 RO
7
ERB7 RO
6
ERB6 RO
5
ERB5 RO
4
ERB4 RO
3
ERB3 RO
2
ERB2 RO
1
ERB1 RO
0
ERB0 RO
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ADM7001
Register Description
4.2.19 Register #1fh - Chip ID (8125)
15
CID33 RO
14
CID32 RO
13
CID31 RO
12
CID30 RO
11
CID23 RO
10
CID22 RO
9
CID21 RO
8
CID20 RO
7
CID13 RO
6
CID12 RO
5
CID11 RO
4
CID10 RO
3
CID03 RO
2
CID02 RO
1
CID01 RO
0
CID00 RO
4.3
4.3.1
Register Description
Control (Register 0h) Bit # Name Description 15 RST RESET 1: PHY Reset 0: Normal operation Setting this bit initiates the software reset function that resets the selected port, except for the phase-locked loop circuit. It will re-latch in all hardware configuration pin values. The software reset process takes 25us to complete. This bit, which is self-clearing, returns a value of 1 until the reset process is complete. 14 LPBK Back Enable 1:Enable loop back mode 0: Disable Loop back mode This bit controls the PHY loop back operation that isolates the network transmitter outputs (TXP and TXN) and routes the MII transmit data to the MII receive data path. This function should only be used when auto negotiation is disabled (bit12 = 0). The specific PHY (10Base-T or 100Base-X) used for this operation is determined by bits 12 and 13. 13 SPEED_LS Speed Selection LSB B 0.60.13 0 0 10 Mbps 0 1 100 Mbps 1 0 1000 Mbps 1 1 Reserved Link speed is selected by this bit or by auto negotiation if bit 12 of this register Type Default Interface R/W 0h 1.Updated by SC MDC/MDIO. 2.Connect to Central Control Block to Generate Reset Signal.
R/W
0h
1.Updated by MDC/MDIO Only. Control the Wire connection in Driver
R/W
1h
When Auto Negotiation is enable, this pin has no effect.
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ADM7001
Bit # Description is set (in which case, the value of this bit is ignored). ANEN Auto Negotiation Enable 1: Enable auto negotiation process 0: Disable Auto negotiation process This bit determines whether the link speed should set up by the auto negotiation process or not. It is set at power up or reset if the PI_RECANEN pin detects a logic 1 input level in Twisted-Pair Mode. PDN Power Down Enable 1: Power Down 0: Normal Operation Ored result with PI_PWRDN pin. Setting this bit high or asserting the PI_PWRDN puts the PHY841F into power down mode. During the power down mode, TXP/TXN and all LED outputs are tri-stated and the MII/RMII interfaces are isolated. ISO Isolate PHY841F from Network 1: Isolate PHY from MII/RMII 0: Normal Operation Setting this control bit isolates the part from the RMII/MII, with the exception of the serial management interface. When this bit is asserted, the PHY841F does not respond to TXD, TXEN and TXER inputs, and it presents a high impedence on its TXC, RXC, CRSDV, RXER, RXD, COL and CRS outputs. ANEN_RS Restart Auto Negotiation T 1: Restart Auto Negotiation Process 0: Normal Operation Setting this bit while auto negotiation is enabled forces a new auto negotiation process to start. This bit is self-clearing and returns to 0 after the auto negotiation process has commenced. DPLX Duplex Mode 1: Full Duplex mode 0: Half Duplex mode If auto negotiation is disabled, this bit Name Type Default
Register Description
Interface
12
R/W
1h
11
R/W
0h
1.Only Access through MDC/MDIO
10
R/W
0h
1.Only Access through MDC/MDIO 2.Used to reset corresponding port.
9
R/W SC
0h
8
R/W
0h
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ADM7001
Bit # Description determines the duplex mode for the link. 7 COLTST Collision Test 1: Enable COL signal test 0: Disable COL signal test When set, this bit will cause the COL signal of MII interface to be asserted in response to the assertion of TXEN. 6 SPEED_M Speed Selection MSB SB Set to 0 all the time indicate that the PHY841F does not support 1000 Mbps function. 5:0 Reserved Not Applicable Name Type Default
Register Description
Interface
R/W
0h
RO
0h
Always 0.
RO
00h
Always 0.
Interface
4.3.2
Status (Register 1h) Bit # Name Description 15 CAP_T4 100Base-T4 Capable Set to 0 all the time to indicate that the PHY841F does not support 100Base-T4 14 CAP_TXF 100Base-X Full Duplex Capable Set to 1 all the time to indicate that the PHY841F does support Full Duplex mode 13 CAP_TXH 100Base-X Half Duplex Capable Set to 1 all the time to indicate that the PHY841F does support Half Duplex mode 12 CAP_TF 10M Full Duplex Capable TP : Set to 1 all the time to indicate that the PHY841F does support 10M Full Duplex mode FX : Set to 0 all the time to indicate that the PHY841F does not support 10M Full Duplex mode 11 CAP_TH 10M Half Duplex Capable TP : Set to 1 all the time to indicate that the PHY841F does support 10M Half Duplex mode FX : Set to 0 all the time to indicate that the PHY841F does not support 10M Half Duplex mode 10 CAP_T2 100Base-T2 Capable Set to 0 all the time to indicate that the PHY841F does not support 100Base-T2 9:7 Reserved Not Applicable
Type Default RO 0h
RO
1h
RO
1h
RO
1h
RO
1h
RO
0h
RO
0h 4-6
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ADM7001
Register Description
Bit # Name Description Type Default Interface RO 1h Use to Control 6 CAP_SUPRMF Preamble Suppression Capable MDC/MDIO This bit is hardwired to 1 indicating that State Machine. the PHY841F accepts management frame without preamble. Minimum 32 preamble bits are required following power-on or hardware reset. One idle bit is required between any two management transactions as per IEEE 802.3u specification. RO 0h Status Updated 5 AN_COMP Auto Negotiation Complete by Auto 1: Auto Negotiation process completed Negotiation 0: Auto Negotiation process not Control Block. completed If auto negotiation is enabled, this bit indicates whether the auto negotiation process has been completed or not. Set to 0 all the time when Fiber Mode is selected. RO 0h Status Updated 4 REM_FLT Remote Fault Detect by Auto 1: Remote Fault detected Negotiation 0: Remote Fault not detected Control Block This bit is latched to 1 if the RF bit in the auto negotiation link partner ability register (bit 13, register address 05h) is set or the receive channel meets the far end fault indication function criteria. It is unlatched when this register is read. RO 1h 3 CAP_ANE Auto Negotiation Ability G 1: Capable of auto negotiation 0: Not capable of auto negotiation TP : This bit is set to 1 all the time, indicating that PHY841F is capable of auto negotiation. FX : This bit is set to 0 all the time, indicating that PHY841F is not capable of auto negotiation in Fiber Mode. RO, 0h Updated By Per 2 LINK Link Status LL port Link 1: Link is up Monitor 0: Link is down This bit reflects the current state of the link -test-fail state machine. Loss of a valid link causes a 0 latched into this bit. It remains 0 until this register is read by the serial management interface.
Infineon ADMtek Co Ltd
4-7
ADM7001
Bit # Name
Register Description
Description Type Default Interface Whenever Linkup, this bit should be read twice to get link up status RO, 0h Updated by Per JAB Jabber Detect LH port Jabber 1: Jabber condition detected Detector 0: Jabber condition not detected RO 1h EXTREG Extended Capability 1: Extended register set 0: No extended register set This bit defaults to 1, indicating that the PHY841F implements extended registers.
1
0
4.3.3 PHY Identifier Register (Register 2h) Bit # Name Description 15:0 PHY- IEEE Address ID[15:0]
Type Default RO 002E
Interface
4.3.4 PHY Identifier Register (Register 3h) Bit # Name Description Type Default 15:10 PHY- IEEE Address/Model No./Rev. No. RO CC10 ID[15:0] 9:4 MODEL[5: INFINEON-ADMTEK CO LTD PHY RO CC10 0] Model ID. 3:0 REV- INFINEON-ADMTEK CO LTD PHY RO 2h ID[3:0] Revision ID. 4.3.5 Advertisement (Register 4h) Bit # Name Description 15 NP Next Page This bit is defaults to 1, indicating that PHY841F is next page capable. 14 Reserved Not Applicable 13 RF Remote Fault 1 Remote Fault has been detected 0 No remote fault has been detected This bit is written by serial management interface for the purpose of communicating the remote fault condition to the auto negotiation link partner. 12 Reserved Not Applicable 11 ASM_DIR Asymmetric Pause Direction Bit[11:10] Capability Type Default R/W 0h
Interface
Interface
RO R/W
0h 0h
S/W should read status from Register 1 (bit 1.4) and fill out this bit during Auto Negotiation in case Remote Fault is detected.
RO R/W
0h 0h
Infineon ADMtek Co Ltd
4-8
ADM7001
Bit # Name Description 00 No Pause 01 Symmetric PAUSE 10 Asymmetric PAUSE toward Link Partner 11 Both Symmetric PAUSE and Asymmetric PAUSE toward local device Pause Operation for Full Duplex Value on PAUREC will be stored in this bit during power on reset. Technology Ability for 100Base-T4 Defaults to 0. 100Base-TX Full Duplex 1: Capable of 100M Full duplex operation 0: Not capable of 100M Full duplex operation 100Base-TX Half Duplex 1: Capable of 100M operation 0: Not capable of 100M operation 10BASE-T Full Duplex 1: Capable of 10M Full Duplex operation 0: Not capable of 10M full duplex operation 10Base-T Half Duplex 1: Capable of 10M operation 0: Not capable of 10M operation Type Default
Register Description
Interface
10
PAUSE
R/W
pin
9 8
T4 TX_FDX
RO R/W
0h 1h Used by Auto Negotiation Block
7
TX_HDX
R/W
1h
6
10_FDX
R/W
1h
Used By Auto Negotiation Block Used By Auto Negotiation Block Used By Auto Negotiation Block
Note: that bit 8:5 should be combined with SPD100, DUPFUL pin input to determine the finalized speed and duplex mode. Used by Auto Negotiation Block. Interface
5
10_HDX
R/W
1h
4:0
Selector These 5 bits are hardwired to 00001b, Field indicating that the PHY841F supports IEEE 802.3 CSMA/CD.
RO
01h
4.3.6 Auto Negotiation Link Partner Ability (Register 5h) Bit # Name Description
Type Default
Infineon ADMtek Co Ltd
4-9
ADM7001
Bit # 15 Name Description NPAGE Next Page 1: Capable of next page function 0: Not capable of next page function ACK Acknowledge 1: Link Partner acknowledges reception of the ability data word 0: Not acknowledged RF Remote Fault 1: Remote Fault has been detected 0: No remote fault has been detected Reserved Not Applicable LP_DIR Link Partner Asymmetric Pause Direction.
Register Description
Type Default Interface RO 0h Updated by Auto Negotiation Block RO 0h Updated by Auto Negotiation Block
14
13
RO
0h
Updated by Auto Negotiation Block Updated by Auto Negotiation Block Updated by Auto Negotiation Block Updated by Auto Negotiation Block Used by Auto Negotiation Block
12 11 10
RO RO RO
0h 0h 0h
9
8
7
6
5
4:0
LP_PAU Link Partner Pause Capability Value on PAUREC will be stored in this bit during power on reset. LP_T4 Link Partner Technology Ability for 100Base-T4 Defaults to 0. LP_FDX 100Base-TX Full Duplex 1: Capable of 100M Full duplex operation 0: Not capable of 100M Full duplex operation LP_HDX 100Base-TX Half Duplex 1: Capable of 100M operation 0: Not capable of 100M operation LP_F10 10BASE-T Full Duplex 1: Capable of 10M Full Duplex operation 0: Not capable of 10M full duplex operation LP_H10 10Base-T Half Duplex 1: Capable of 10M operation 0: Not capable of 10M operation Selector Encoding Definitions. Field
RO
0h
RO
1h
RO
1h
RO
1h
Used By Auto Negotiation Block Used By Auto Negotiation Block Used By Auto Negotiation Block Updated By Auto Negotiation Block.
RO
1h
RO
01h
4.3.7
Auto Negotiation Expansion Register (Register 6h) Bit # Name Description 15:5 Reserved Not Applicable 4 PFAULT Parallel Detection Fault
Type Default Interface RO 000h 000h RO, 0h Updated by Auto
Infineon ADMtek Co Ltd
4-10
ADM7001
Bit # Description 1: Fault has been detected 0: No Fault Detect LPNPABL Link Partner Next Page Able E 1: Link Partner is next page capable 0: Link Partner is not next page capable NPABLE Next Page Able 0: Next page Disable 1: Next page Enable. PGRCV Page Received 1: A new page has been received 0: No new page has been received Name
Register Description
Type Default Interface LH Negotiation Block RO 0h Updated By Auto Negotiation Block RO 0h
3
2
1
RO, LH RO
0h
0
LPANABL Link Partner Auto Negotiation Able E 1: Link Partner is auto negotiable 0: Link Partner is not auto negotiable
0h
Updated By Auto Negotiation Block Updated By Auto Negotiation Block
Interface
4.3.8
Register Reserved (Register 7h-Fh) Bit # Name Description 15:0 Reserved
Type Default
4.3.9
Generic PHY Configuration Register (Register 10h) Note: PHY Control/Configuration Registers start from address 16 to 21. Interface
Bit # Name Description Type Default 15:14 IFSEL[1:0] Interface Select. Value on RMII_EN and RO 1h GPSI will be stored in IFSEL[1] and IFSEL[0], respectively. 00: MII 01: GPSI 1x : RMII 13:12 LBKMD[1: Loop Back Mode Select. When 0.14 R/W 0h 0] LPBK is set to 1, these two bits are set to 01 by default. Value on these two bits can be modified through MDC/MDIO. When 0.14 LPBK is set to 0, these two bits are reset to 00 and can't be updated by MDC/MDIO. 00 : Disable Loop back
01 : PCS Layer Loop back mode
10 : PMA Layer Loop back mode
11 : PMD layer loop back mode Note : Both 10M and 100M loopback should be
Infineon ADMtek Co Ltd
4-11
ADM7001
Bit # Name Description
covered by AD2106.
Register Description
Type Default Interface
11:10 Reserved Not Applicable 9 FLTLED Enable colled output remote fault status 0: Disable 1: Enable. 8 CONV Converter mode (only valid in rmii mode) 0:normal mode 1:converter mode 7:5 Reserved Not Applicable 4 XOVEN Cross Over Auto Detect Enable. 0: Disable 1: Enable 3:2 Reserved Infineon-ADMtek Co Ltd reserved bits. Writing value other than 0 to these two bits may cause abnormal operation. 1 ENREG8 Enable Register 8 to Store Next Page Information. 1 - Store Next Page in Register 8 0 - Store Next Page in Register 5 0 DISPMG Disable Power Management Feature. 0: Enable. Enable Medium Detect Function. 1: Disable. Medium_On is high all the time.
RO R/W R/W RO R/W
0h 0h 0h 0h pin
~DIS_AMDIX
R/W R/W
0h 1h Only Available when Auto Negotiation Enabled.
R/W
0h
4.3.10 PHY 10M Module Configuration Register (Register 11h) Bit # Name Description Type Default Interface 15 Reserved RO 0h 14 SERIAL 10BASE-T Serial Mode Select. Only R/W 0h GPSI Recommend available when AD2106 works in 10M Value mode. 0 : 10M MII or RMII mode (According to RMII_EN) 1 : 10M Serial Mode (Seven Wire Mode) R/W 1h 13 Reserved Infineon-ADMtek Co Ltd reserved bits. Writing value other than 1 to this bit may cause abnormal operation. R/W 0h 12:11 Reserved Infineon-ADMtek Co Ltd reserved bits. Writing value other than 0 to these two bits may cause abnormal operation. R/W 1h 10 INTCHKE Polarity Interval Timer Check Enable. 1 = Enable N 0 = Disable Reserved Infineon-ADMtek Co Ltd reserved bits. 9 R/W 1h
Infineon ADMtek Co Ltd
4-12
ADM7001
Bit # Name Description Writing value other than 1 to this bit may cause abnormal operation. Infineon-ADMtek Co Ltd reserved bits. Writing value other than 5 to these three bits may cause abnormal operation. Infineon-ADMtek Co Ltd reserved bits. Writing value other than 1 to this bit may cause abnormal operation. Auto Polarity Disable 1: Auto Polarity Function Disabled 0: Normal Enable Receive Jabber Monitor. 0: Disable 1: Enable Disable Transmit Jabber 1: Disable Transmit Jabber Function 0: Enable Transmit Jabber Function Normal Threshold 0: Lower 10BASE-T Receive threshold 1: Normal 10BASE-T Receive threshold Force 10M Receive Good Link 1: Force Good Link 0: Normal Operation Type Default
Register Description
Interface
8:6 5 4
Reserved Reserved APDIS
R/W R/W R/W
5h 0h 0h
3
ENRJAB
R/W
1h
2
DISTJAB
R/W
0h
1
NTH
R/W
0h
0
FGDLNK
R/W
0h
4.3.11 PHY 100M Module Control Register (Register 12h) Bit # Name Description 15:12 Reserved 11:10 Reserved Infineon-ADMtek Co Ltd reserved bits. Writing value other than 0 to these two bits may cause abnormal operation. 9:8 Reserved Infineon-ADMtek Co Ltd reserved bits. Writing value other than 0 to these two bits may cause abnormal operation. 7 SELFX Fiber Select 1: Fiber Mode 0: TP Mode 6:5 Reserved Infineon-ADMtek Co Ltd reserved bits. Writing value other than 0 to these two bits may cause abnormal operation. 4 DISSCR Disable Scrambler 1: Disable Scrambler 0: Enable Scrambler When set to fiber mode, this bit will be
Type Default RO 0h R/W 0h
Interface
R/W R/W
00h pin FXEN
R/W R/W
1h pin When programmed to fiber mode, set to 1 automatically 4-13
Infineon ADMtek Co Ltd
ADM7001
Bit # Description forced to 1 automatically. Write 0 to this bit in Fiber Mode has no effect. ENFEFI Enable FEFI 1: Enable FEFI 0: Disable FEFI DIS_CABL Disable cable length led indication EN_LED When this bit is set to 0, SPDLED, COLLED
and LNKACTLED are used to represent twisted pair cable length. See SPDLED description for more detail
Register Description
Name Type Default Interface
3
R/W
0h
2
RO
1h
1 0
1'b1 : disable cable length led 1'b0 : enable cable length led INTR_ACT Interrupt active value control 1: active low IVE 0: active low Reserved Infineon-ADMtek Co Ltd reserved bits. Writing value other than 0 to this bit may cause abnormal operation.
R/W R/W
1h 0h
4.3.12 LED Configuration Register (Register 13h) Bit # Name Description 15:12 Reserved 11:8 LNKCTRL Link/Act LED Control. 0000: Collision 0001: All Errors 0010: Duplex 0011: Duplex/Collision 0100: Speed 0101: Link 0110: Transmit Activity 0111: Receive Activity 1000: TX/RX Activity 1001: Link/Receive Activity 1010: Link and TX/RX Activity 1011: 100M False Carrier Error/10M Receive Jabber 1100: 100M Error End of Stream/10M Transmit Jabber 1101: Reserved 1110: Distance (See LED Description for more detail) 7:4 COLCTRL COLLISION LED Control. 0000: Collision
Type Default RO 0h RO 1010
Interface
RO
0000
Infineon ADMtek Co Ltd
4-14
ADM7001
Bit # Description 0001: All Errors 0010: Duplex 0011: Duplex/Collision 0100: Speed 0101: Link 0110: Transmit Activity 0111: Receive Activity 1000: TX/RX Activity 1001: Link/Receive Activity 1010: Link and TX/RX Activity 1011: 100M False Carrier Error/10M Receive Jabber 1100: 100M Error End of Stream/10M Transmit Jabber 1101: Reserved 1110: Distance (See LED Description for more detail) SPDCTRL Speed LED Control. 0000: Collision 0001: All Errors 0010: Duplex 0011: Duplex/Collision 0100: Speed 0101: Link 0110: Transmit Activity 0111: Receive Activity 1000: TX/RX Activity 1001: Link/Receive Activity 1010: Link and TX/RX Activity 1011: 100M False Carrier Error/10M Receive Jabber 1100: 100M Error End of Stream/10M Transmit Jabber 1101: reserved 1110: Distance (See LED Description for more detail) Name Type Default
Register Description
Interface
3:0
RO
0100
4.3.13 Interrupt Enable Register (Register 14h) Bit # Name Description 15:10 Reserved 9 XOVCHG Cross Over mode Changed Interrupt Enable 1: Interrupt Enable 0: Interrupt Disable 8 SPDCHG Speed Changed Interrupt Enable
Type Default RO 00h R/W 1h
Interface
R/W
1h 4-15
Infineon ADMtek Co Ltd
ADM7001
Bit # Name Description 1: Interrupt Enable 0: Interrupt Disable Duplex Changed Interrupt Enable 1: Interrupt Enable 0: Interrupt Disable Page Received Interrupt Enable 1: Interrupt Enable 0: Interrupt Disable Link Status Changed Interrupt Enable 1: Interrupt Enable 0: Interrupt Disable Symbol Error Interrupt Enable 1: Interrupt Enable 0: Interrupt Disable False Carrier Interrupt Enable 1: Interrupt Enable 0: Interrupt Disable Transmit Jabber Interrupt Enable 1: Interrupt Enable 0: Interrupt Disable Receive Jabber Interrupt Enable 1: Interrupt Enable 0: Interrupt Disable Error End of Stream Enable 1: Interrupt Enable 0: Interrupt Disable Type Default
Register Description
Interface
7 6 5 4 3 2 1 0
DUPCHG PGRCHG LNKCHG SYMERR FCAR TJABINT RJABINT ESDERR
R/W R/W R/W R/W R/W R/W R/W R/W
1h 1h 1h 1h 1h 1h 1h 1h
4.3.14 PHY Generic Status Register (Register 16h) Note: PHY Status Registers start from 22 to 28 (29 to 30 reserves for further use) Bit # Name Description Type Default Interface 15:14 Reserved RO 00h 13:11 Reserved Not Applicable 10 MD 0h Medium Detect. Real Time Status for RO Medium_Detect Signal 0: Medium_Detect Fail 1: Medium_Detect Pass pin FXEN 9 FXEN Fiber Enable. Only Changed when PHY RO Reset 0: TX 1: FX mode OR'ed result of FXEN and 17.9 (SELFX) 8 XOVER Cross Over status. RO 0h 0: MDI mode
Infineon ADMtek Co Ltd
4-16
ADM7001
Bit # Description 1: MDIX mode CBLEN Cable Length. Only valid for 100M MSB is IC0 8'h1a: 40 meters 8'h22: 60 meters 8'h94: 80 meters 8'h9a: 100 meters 8'ha2: 120 meters 8'hab: 140 meters Name Type Default
Register Description
Interface
7:0
RO
00h
4.3.15 PHY Specific Status Register (Register 17h) Bit # Name Description 15:12 Reserved
11 10 9
8
7
6
5
4
JAB-RX Real Time 10M Receive Jabber Status 1: Jabber 0: No jabber JAB_TX Real Time 10M Transmit Jabber Status 1:Jabber 0: No Jabber POLAR Polarity. Only available in 10M 0: Normal Polarity 1: Polarity Reversed PAUOUT Pause Out capability. Disabled when Half Duplex. 0: Lack of Pause Out capability 1: Has Pause Out capability PAUIN Pause In capability. Disabled when Half Duplex. 0: Lack of Pause In capability 1: Has Pause In capability DUPLEX Operating Duplex 1: Full Duplex 0: Half Duplex SPEED Operating Speed 1: 100Mb/s 0: 10Mb/s LINK Real Time Link Status 1: Link Up 0: Link Down
Type Default Interface RO 0h Force to 0 all the time. RO 0h
RO RO
0h 0h
Updated by 10M Block
RO
0h
RO
0h
RO
1h
RO
1h
RO
0h
Infineon ADMtek Co Ltd
4-17
ADM7001
Bit # Name Description 3 RECPAU Pause Recommend Value. Only Changed when PHY Reset. This bit is disabled automatically when RECDUP is 0. 0: Pause Disable 1: Pause Enable 2 RECDUP Duplex Recommended Value. Only Changed when PHY Reset 1: Full Duplex 0: Half Duplex 1 RECSPD Speed Recommend Value. Only Changed when PHY Reset 1: 100M 0: 10M 0 RECANEN Recommended Auto Negotiation Value. Only Changed when PHY Reset 4.3.16 PHY Recommend Value Status Register (Register 18h) Bit # Name Description 15 Reserved Not Applicable 14 RECAN Auto Negotiation Recommend Value 13 SELFX Fiber Select Recommend Value 12 REC100 Speed Recommend Value 0: 10M 1: 100M 11 RECFUL Duplex Recommend Value. 0: Half Duplex 1: Full Duplex 10 PAUREC Pause Capability Recommend Value 1: Pause Enable 0: Pause Disable 9 DISFEFI Far End Fault Disable. 0: Enable 1: Disable 8 XOVEN Cross Over Capability Recommend Value. 0: Disable 1: Enable 7 XOVER Cross Over Status. 0: Non-Cross Over 1: Cross Over Type Default RO pin
Register Description
Interface
RO
pin
DUPFUL
RO
pin
SPD100
RO
pin
ANEN
Type Default RO pin RO pin RO pin RO pin
Interface
RO
pin
RO
1'b0
RO
1'b0
RO
Pin
RO
0h
Infineon ADMtek Co Ltd
4-18
ADM7001
Bit # Name Description 6 RMII_SMII RMII_SMII Interface 1: RMII or SMII Interface used 0: Non RMII_SMII Interface 5 REPEATE Repeater Mode Recommend Value R 1: Repeater 0: NIC/SW 4:0 PHYA PHY Address 4.3.17 Interrupt Status Register (Register 19h) Bit # Name Description 15:10 Reserved 9 XOVCHG Cross Over mode Changed 1: Cross Over mode Changed 0: Cross Over mode Not Changed 28 SPDCHG Speed Changed 1: Speed Changed 0: Speed Not Changed 7 DUPCHG Duplex Changed 1: Duplex Changed 0: Duplex not changed 6 PGRCHG Page Received 1: Page Received 0: Page not received 5 LNKCHG Link Status Changed 1:Link Status Changed 0: Link Status not Changed 4 SYMERR Symbol Error 1: Symbol Error 0: No symbol Error 3 FCAR False Carrier 1: False Carrier 0: No false carrier Note: high whenever Link is Failed. 2 TJABINT Transmit Jabber 1: Jabber 0: No Jabber 1 RJABINT Receive Jabber 1: Jabber 0: No Jabber 0 ESDERR Error End of Stream 1: ESD Error 0: No ESD Error Type Default RO Pin
Register Description
Interface
RO RO
Pin 01h
Type Default Interface COR 00h COR 0h Updated By PMD Block
COR COR COR COR COR COR
0h 0h 0h 0h 0h 0h
Updated By Auto Negotiation Block Updated By Auto Negotiation Block Updated By Auto Negotiation Block Updated By Auto Negotiation Block Updated By 100M Block Updated By 100M Block Updated By 10M Block Updated By 10M Block Updated By 100M Block
COR COR COR
0h 0h 0h
Infineon ADMtek Co Ltd
4-19
ADM7001
4.3.18 Receive Error Counter Register (Register 1Dh) Bit # Name Description 15:0 ERB[15:0] Error Counter. Includes 1.100M False Carrier 2.100M Symbol Error 3.10M Transmit Jabber 4.10M Receive Jabber 5.Error Start of Stream 6.Error End of Stream
Register Description
Type Default RO 0000h
Interface
4.3.19 Chip ID Register (Register 1Fh) Bit(s) Name Description 15:0 CHIPID[15:Infineon-ADMtek Co Ltd CHIP ID 0]
R/W Default RO 8125
Interface
Infineon ADMtek Co Ltd
4-20
ADM7001
Electrical Specification
Chapter 5
5.1
Electrical Specification
DC Characterization
Rating 3.0 to 3.6 2.25 to 2.75 -0.3 to VCC33 + 0.3 -0.25 to Vcc25 + 0.25 -55 to 155 2000 0.5 Units V V V V C V W
5.1.1 Absolute Maximum Rating Symbol Parameter VCC33 3.3V Power Supply VCC25 2.5V Power Supply VIN Input Voltage Vout Output Voltage TSTG Storage Temperature ESD ESD Rating PC Power Consumption
Table 5-1 Electrical Absolute Maximum Rating
5.1.2 Recommended Operating Conditions Symbol Parameter VCC33 Power Supply Vin Input Voltage Tj Junction Operating Temperature
Min 3.135 0 0
Typ 3.3 25
Max 3.465 VCC33 115
Units V V C
Table 5-2 Recommended Operating Conditions
5.1.3
DC Electrical Characteristics for 2.5V Operation (Under Vcc=3.0V~3.6V, Tj= 0 C ~ 115 C ) Conditions Min Symbol Parameter VIL Input Low Voltage CMOS VIH Input High Voltage CMOS 0.7 * Vcc VOL Output Low Voltage CMOS VOH Output High Voltage CMOS 2.0 RI Input Pull_up/down VIL=0V or Resistance VIH = VCC33
Typ
75
Max Units 0.3 * Vcc V V 0.4 V V K
Table 5-3 DC Electrical Characteristics for 2.5V Operation
Infineon ADMtek Co Ltd
5-1
ADM7001
Electrical Specification
5.2
AC Characterization
5.2.1 XI/OSCI (Crystal/Oscillator) Timing (In MII Mode)
t_XI_PER t_XI_HI t_XI_LO
VIH_XI VIL_XI
t_XI_RISE t_XI_FALL
Figure 5-1 Crystal/Oscillator Timing
Symbol t_XI_PER
Description XI/OSCI Clock Period (Note-1)
MIN TYP 40.0 - 40.0 50ppm
T_XI_HI T_XI_LO T_XI_RISE T_XI_FALL
XI/OSCI Clock High XI/OSCI Clock Low XI/OSCI Clock Rise Time , VIL (max) to VIH (min) XI/OSCI Clock Fall Time , VIH (min) to VIL (max)
14 14
20.0 20.0
MAX UNIT 40.0 + ns 50pp m ns ns 4 ns
4
ns
Table 5-4 Crystal/Oscillator Timing
Note-1 : Clock period less then 40ns - 50ppm or greater than 40ns + 50ppm may introduce peer receive CRC due to insufficient receive FIFO depth. Check peer receive FIFO description to confirm.
Infineon ADMtek Co Ltd
5-2
ADM7001
Electrical Specification
5.3
5.3.1
RMII Timing
REFCLK Input Timing (XI in RMII Mode)
t_IN50_PER t_IN50_HI t_IN50_LO
VIH_RMII VIL_RMII
t_IN50_RISE t_IN50_FALL
Figure 5-2 REFCLK Input Timing
Symbol t_IN50_PER
Description REFCLK Clock Period
MIN TYP 20.0 - 20.0 50ppm
t_IN50_HI t_IN50_LO t_IN50_RISE t_IN50_FALL
REFCLK Clock High REFCLK Clock Low REFCLK Clock Rise Time , VIL (max) to VIH (min) REFCLK Clock Fall Time , VIH (min) to VIL (max)
Table 5-5 REFCLK Input Timing
8 8
10.0 10.0
MAX UNIT 20.0 + ns 50pp m ns ns 2 ns
2
ns
Infineon ADMtek Co Ltd
5-3
ADM7001
5.3.2 REFCLK Output Timing (CLKO50 in RMII Mode)
Electrical Specification
t_OUT50_PER t_OUT50_HI t_OUT50_LO
VIH_RMII VIL_RMII
t_OUT50_RISE t_OUT50_FALL
Figure 5-3 REFCLK Output Timing
Symbol t_OUT50_PER
Description REFCLK Clock Period
MIN TYP 20.0 - 20.0 50ppm
t_OUT50_HI REFCLK Clock High t_OUT50_LO REFCLK Clock Low t_OUT50_RISE REFCLK Clock Rise Time , VIL (max) to VIH (min) t_OUT50_FALL REFCLK Clock Fall Time , VIH (min) to VIL (max) t_OUT50_JIT REFCLK Clock Jittering (p-p)
Table 5-6 REFCLK Output Timing
8 8
10.0 10.0
MAX 20.0 + 50pp m 12 12 2
UNIT ns
ns ns ns ns ns
2 0.15
Infineon ADMtek Co Ltd
5-4
ADM7001
5.3.3 RMII Transmit Timing
Electrical Specification
REFCLK
TXEN
t_RT_DSETUP t_RT_DHOLD
TXD
PREAM
PREAM
TXD0
TXD1
TXD2
TXD3
TXD4
TXD5
TXDN
00
00
t_RT_TXE2MH t_RT_TXE2ML DATA On Medium
Figure 5-4 RMII Transmit Timing
Symbol t_RT_DSETUP t_RT_DHOLD t_RT_TXE2MH1
00
Description TXD to REFCLK Rising Setup Time TXD to REFCLK Rising Hold Time TXEN asserts to data transmit to medium
MIN 2 2
TYP
MAX UNIT ns ns 235 ns
t_RT_TXE2MH1 TXEN asserts to data transmit to medium
0
1550 ns 260
ns
t_RT_TXE2ML10 TXEN de-asserts to finish transmitting
0
t_RT_TXE2ML10 TXEN de-asserts to finish transmitting
Table 5-7 RMII Transmit Timing
1250 ns
Infineon ADMtek Co Ltd
5-5
ADM7001
5.3.4 RMII Receive Timing
REFCLK NON_IDLE (Internal) CRSDV
t_RR_CSH2DAT t_RR_DDLY
PREAM
Electrical Specification
t_RR_ML2CSL t_RR_MH2CSH
t_RR_CSL2DAT
RXD
PREAM
RXD0
RXD1
RXD2
RXD4
RXD5
RXD6
RXDN
00
Figure 5-5 RMII Receive Timing
Symbol Description t_RR_MH2CSH1 Signal Detected on Medium to CRSDV High
00
MIN
TYP
MAX UNIT 265 ns
t_RR_MH2CSH1 Signal Detected on Medium to CRSDV High
0
1000 ns 260 570 160 ns ns ns
t_RR_ML2CSL10 IDLE Detected on Medium to CRSDV low
0
t_RR_ML2CSL10 IDLE Detected on Medium to CRSDV low t_RR_CSH2DAT CRSDV High to Receive Data on RXD
100
t_RR_CSH2DAT CRSDV High to Receive Data on RXD
10
1600 ns 160 1600 5 ns ns ns
t_RR_CSL2DAT CRSDV Toggle to End of Data Receiving
100
t_RR_CSL2DAT CRSDV Toggle to End of Data Receiving
10
t_RR_DDLY
REFCLK Rising to RXD/CRSDV Delay Time
Table 5-8 RMII Receive Timing
Infineon ADMtek Co Ltd
5-6
ADM7001
Electrical Specification
5.4
5.4.1
MII Timing
RXCLK Clock Timing
t_RCK_PER t_RCK_HI t_RCK_LO
VIH_MII VIL_MII
t_RCK_FALL
RXCLK
t_RCK_RISE
Figure 5-6 RXCLK Output Timing
Symbol t_RCK_PER100
Description RXCLK Clock Period (100M) (Note-1)
MIN TYP 40.0 - 40.0 50ppm
t_RCK_PER10 t_RCK_HI100 t_RCK_HI10 t_RCK_LO100 t_RCK_LO10 t_RCK_RISE t_RCK_FALL t_RCK_JIT
RXCLK Clock Period (10M) (Note-1) RXCLK Clock High (100M) RXCLK Clock High (10M) RXCLK Clock Low (100M) RXCLK Clock Low (10M) RXCLK Clock Rise Time , VIL (max) to VIH (min) RXCLK Clock Fall Time , VIH (min) to VIL (max) REFCLK Clock Jittering (p-p)
Table 5-9 RXCLK Output Timing
400 400 50ppm 16 200 16 200
MAX 40.0 + 50pp m 400 + 50pp m 24
UNIT ns
ns ns ns ns ns ns ns ns
24 2 2 0.15
Note -1 : Clock period ppm value is highly depended upon peer transmitter clock source skew.
Infineon ADMtek Co Ltd
5-7
ADM7001
Electrical Specification
5.4.2
MII Receive Timing
RXCLK Carrier Detect on Medium CRS
t_MR_MH2DAT t_MR_ML2DAT
t_MR_MH2CSH
t_MR_ML2CSL
RXDV
t_MR_DDLY
RXD
0000
0000
0000
PREAM
PREAM
SFD
RXD
RXD
RXD
RXD
0000
Figure 5-7 MII Receive Timing
Symbol Description t_MR_MH2CSH1 Signal Detected on Medium to CRS High
00
MIN
TYP
MAX UNIT 140 ns
t_MR_MH2CSH1 Signal Detected on Medium to CRS High
0
1450 150 2300 10 10 25 25 120 235 150 1450
ns ns ns ns ns ns ns ns ns
t_MR_MH2DAT Signal Detected on Medium to RXDV High
100
t_MR_MH2DAT Signal Detected on Medium to RXDV High
10
t_MR_DDLY100 RXCLK rising to Data Valid Delay Time t_MR_DDLY10 RXCLK rising to Data Valid Delay Time T_MR_ML2CSL IDLE Detected on Medium to CRS Low
100
T_MR_ML2CSL IDLE Detected on Medium to CRS Low
10
T_MR_ML2DAT IDLE Detected on Medium to RXDV Low
100
T_MR_ML2DAT IDLE Detected on Medium to RXDV Low
10
Table 5-10 MII Receive Timing
Infineon ADMtek Co Ltd
5-8
ADM7001
Electrical Specification
5.4.3
TXCLK Output Timing
t_TCK_PER t_TCK_HI t_TCK_LO
VIH_MII VIL_MII
t_TCK_FALL
TXCLK
t_TCK_RISE
Figure 5-8 TXCLK Output Timing
Symbol t_TCK_PER100
Description TXCLK Clock Period (100M)
MIN TYP 40.0 - 40.0 50ppm
t_TCK_PER10 t_TCK_HI100 t_TCK_HI10 t_TCK_LO100 t_TCK_LO10 t_TCK_RISE t_TCK_FALL t_TCK_JIT
TXCLK Clock Period (10M) TXCLK Clock High (100M) TXCLK Clock High (10M) TXCLK Clock Low (100M) TXCLK Clock Low (10M) TXCLK Clock Rise Time , VIL (max) to VIH (min) TXCLK Clock Fall Time , VIH (min) to VIL (max) TXCLK Clock Jittering (p-p)
Table 5-11 TXCLK Input Timing
400 400 50ppm 16 160 16 160
MAX 40.0 + 50pp m 400 + 50pp m 24 240 24 240 2
UNIT ns
ns ns ns ns ns ns ns ns
2 0.15
Infineon ADMtek Co Ltd
5-9
ADM7001
Electrical Specification
5.4.4
MII Transmit Timing
TXCLK
TXEN
t_MT_DSETUP
t_MT_DHOLD
TXD DATA on Medium
0000
PREAM
PREAM
SFD
TXD
TXD
TXD
TXD
TXD
0000
0000
t_MT_TXE2MH
t_MT_TXE2ML
t_MT_TXE2CSH
t_MT_TXECSL
CRS
(Half Duplex Only)
Figure 5-9 MII Transmit Timing
Description TXD to TXCLK Rising Setup Time TXD to TXCLK Rising Hold Time TXEN asserts to data transmit to medium (100M) 00 t_MT_TXE2MH1 TXEN asserts to data transmit to medium (10M) 0 t_MT_TXE2CSH TXEN asserts to CRS Assert (100M Half)
100
Symbol t_MT_DSETUP t_MT_DHOLD t_MT_TXE2MH1
MIN 10 10
TYP
MAX 25 25 75
UNIT ns ns ns ns ns ns ns ns ns ns
350 15 200 95 660 15 190
t_MT_TXE2CSH TXEN asserts to CRS Assert (10M Half)
10
t_MT_TXE2ML1 TXEN de-asserts to finish transmitting (100M)
00
t_MT_TXE2ML1 TXEN de-asserts to finish transmitting (10M)
0
t_MT_TXECSL10 TXEN de-asserts to CRS de-asserts (100M)
0
t_MT_TXECSL10 TXEN de-asserts to CRS de-asserts (10M)
Table 5-12 MII Transmit Timing
Infineon ADMtek Co Ltd
5-10
ADM7001
Electrical Specification
5.5
5.5.1
GPSI Timing
GPSI Receive Timing
t_GPSI_RCK_PER t_GPSI_RCK_HI t_GPSI_RCK_LO
RXCLK Carrier Detect on Medium CRS
t_GR_MH2DAT t_GR_DDLY
t_GR_MH2CSH
t_GR_ML2CSL
RXD
0
0
0
PREAM
PREAM
SFD
RXD
RXD
RXD
RXD
0
Figure 5-10 GPSI Receive Timing
Symbol t_GPSI_RCK_PE R t_GPSI_RCK_HI t_GPSI_RCK_L O t_GR_MH2CSH t_GR_MH2DAT t_GR_DDLY T_GR_ML2CSL
Description 10M Receive Clock Period
10M Receive Clock High 10M Receive Clock Low Signal Detected on Medium to CRS High Signal Detected on Medium to Data Valid RXCLK rising to Data Valid Delay Time IDLE Detected on Medium to CRS Low
Table 5-13 GPSI Receive Timing
MIN TYP 100 100 50ppm 40 40
MAX UNIT 100 + ns 50ppm ns ns
40
1500 1600 60 230
ns ns ns ns
Infineon ADMtek Co Ltd
5-11
ADM7001
5.5.2 GPSI Transmit Timing
t_GPSI_TCK_PER t_GPSI_TCK_HI t_GPSI_TCK_LO
Electrical Specification
TXCLK
TXEN
t_GT_DSETUP
t_GT_DHOLD
TXD DATA on Medium
0
PREAM
PREAM
SFD
TXD
TXD
TXD
TXD
TXD
0
0
t_GT_TXE2MH
t_GT_TXE2ML
t_GT_TXE2CSH
t_GT_TXECSL
CRS
(Half Duplex Only)
Figure 5-11 GPSI Transmit Timing
Symbol t_GPSI_TCK_PE R t_GPSI_TCK_HI t_GPSI_TCK_L O t_GT_DSETUP t_GT_DHOLD t_GT_TXE2MH t_GT_TXE2CSH t_GT_TXE2ML t_GT_TXECSL
Description 10M Transmit Clock Period
10M Transmit Clock High 10M Transmit Clock Low TXD to TXCLK Rising Setup Time TXD to TXCLK Rising Hold Time TXEN asserts to data transmit to medium TXEN asserts to CRS Assert (Half) TXEN de-asserts to finish transmitting TXEN de-asserts to CRS de-asserts
Table 5-14 GPSI Transmit Timing
MIN TYP 100 100 50ppm 40 40
MAX UNIT 100 + ns 50ppm ns ns Ns ns ns ns ns ns
40 40 150 10 900 10
Infineon ADMtek Co Ltd
5-12
ADM7001 5.6 Serial Management Interface (MDC/MDIO) Timing
Electrical Specification
t_MDC_PER
t_MDC_LO
t_MDC_HI
MDC
t_MDIO_DLY
MDIO(Output)
MDC
t_MDIO_SETUP t_MDIO_HOLD
MDIO(Input)
Figure 5-12 Serial Management Interface (MDC/MDIO) Timing
Symbol t_MDC_PER t_MDC_HI t_MDC_LO t_MDIO_DLY t_MDIO_SETUP t_MDIO_HOLD
Description MDC Period MDC High MDC High MDC to MDIO Delay Time MDIO Input to MDC Setup Time MDIO Input to MDC Hold Time
MIN 100 40 40
TYP
10 10
MAX UNIT ns ns ns 20 ns ns ns
Table 5-15 Serial Management Interface (MDC/MDIO) Timing
Infineon ADMtek Co Ltd
5-13
ADM7001
Electrical Specification
5.6
Power On Configuration Timing
VCC3IN VCC25OUT RESET#
t_V33_V25 t_V25_RST t_RST_PW
XI/OSCI
t_PL_DHOLD t_PL_DSETUP
PWR ON LATCH
Figure 5-13 Power On Configuration Timing
Symbol t_V33_V25 t_V25_RST t_RST_PW t_PL_DSETUP t_PL_DHOLD
Description 3.3V Power Good to 2.5V Power Good Hardware Reset With Device Powered up Hardware Reset With Clock Running Reset High to Configuration Setup Time Reset High to Configuration Hold Time
MIN TBD 200 800 200 0
TYP
MAX UNIT ms ms ns ns ns
Table 5-16 Power On Configuration Timing
Infineon ADMtek Co Ltd
5-14
ADM7001
Packaging
Chapter 6
6.1
Packaging
ADM7001 Low Profile Quad Flat Package (LQFP) 48 Pin
Infineon ADMtek Co Ltd
6-1

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